lan9211 Standard Microsystems Corp., lan9211 Datasheet - Page 130

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lan9211

Manufacturer Part Number
lan9211
Description
Lan9211 High-performance Small Form Factor Single-chip Ethernet Controller With Hp Auto-mdix Support
Manufacturer
Standard Microsystems Corp.
Datasheet

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Revision 2.3 (08-06-08)
6.3
SYMBOL
nCS, nRD
t
t
t
t
t
t
t
t
csdv
acyc
t
asu
adv
don
doff
doh
csh
A[7:5]
A[4:1]
Data Bus
ah
In this mode, performance is improved by allowing up to 16 WORD read cycles back-to-back. PIO
Burst Reads can be performed using Chip Select (nCS) or Read Enable (nRD). Either or both of these
control signals must go high between bursts for the period specified.
Note: The “Data Bus” width is 16 bits
Note: A PIO Burst Read cycle begins when both nCS and nRD are asserted. The cycle ends when
PIO Burst Reads
DESCRIPTION
nCS, nRD Deassertion Time
nCS, nRD Valid to Data Valid
Address Cycle Time
Address Setup to nCS, nRD valid
Address Stable to Data Valid
Address Hold Time
Data Buffer Turn On Time
Data Buffer Turn Off Time
Data Output Hold Time
either or both nCS and nRD are deasserted. They may be asserted and deasserted in any
order.
Figure 6.2 PIO Burst Read Cycle Timing
Table 6.4 PIO Burst Read Timing
DATASHEET
High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Support
130
MIN
13
45
0
0
0
0
TYP
MAX
30
40
7
SMSC LAN9211
Datasheet
UNITS
ns
ns
ns
ns
ns
ns
ns

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