lan9303 Standard Microsystems Corp., lan9303 Datasheet - Page 53

• Manufacturer Part Number: lan9303
• Description: Small Form Factor Three Port 10/100 Managed Ethernet Switch With Single Mii/rmii/turbo Mii
• Manufacturer: Standard Microsystems Corp.

Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII
Datasheet
SMSC LAN9303/LAN9303i
P0_mode_strap[1:0]
P0_rmii_clock_dir_strap
P0_clock_strength_strap
turbo_mii_enable_strap_0
phy_addr_sel_strap
led_pol_strap[5:0]
STRAP NAME
Note 4.1
Table 4.3 Hard-Strap Configuration Strap Definitions (continued)
This pin has shared strap functionality. Refer to
Port 0 Mode Strap: Configures the default mode of
operation for Port 0.
00 = MII MAC Mode
01 = MII PHY Mode
10 = RMII PHY Mode
11 = RESERVED
These operating modes result from the following mapping:
Refer to
additional information on the various modes of the device.
Port 0 RMII Clock Direction Strap: Configures the default
value of the
Special Control/Status Register
(VPHY_SPECIAL_CONTROL_STATUS).
Port 0 Clock Strength Strap: Configures the default value
of the
Special Control/Status Register
(VPHY_SPECIAL_CONTROL_STATUS).
Port 0 Turbo MII Enable Strap: Configures the default
value of the
Control/Status Register
(VPHY_SPECIAL_CONTROL_STATUS)
mode.
PHY Address Select Strap: Configures the default MII
management address values for the PHYs and Virtual PHY
as detailed in
LED Polarity Strap: Configures the default polarity for
each of the LEDs when they are an open-drain or open-
source output.
0 = The LED is set as active high, since it is assumed
that a LED to ground is used as the pull-down.
1 = The LED is set as active low, since it is assumed
that a LED to VDD is used as the pull-up.
001, 010, or 011
100, 101, or 110
P0_MODE[2:0]
RMII/Turbo MII Clock Strength
Section 2.3, "Modes of Operation," on page 19
000
111
Turbo MII Enable
RMII Clock Direction
Section 7.1.1, "PHY Addressing," on page
DATASHEET
DESCRIPTION
53
P0_mode_strap[1:0]
bit of the
10 (RMII PHY)
00 (MII MAC)
01 (MII PHY)
RESERVED
bit of the
bit of the
Virtual PHY Special
when in MII PHY
Table 4.4
Virtual PHY
Virtual PHY
for details.
for
88.
P0_MODE2 :
P0_MODE1 :
P0_MODE0
P0_MODE1
P0_MODE0
P0_MODE1
PHYADDR_LED5P
PHYADDR_LED5P
MNGT1_LED4P :
MNGT0_LED3P :
E2PSIZE_LED2P :
AMDIX2_LED1P :
AMDIX1_LED0P
Revision 1.3 (08-27-09)
Note 4.1
PIN(S)
: