lan9303 Standard Microsystems Corp., lan9303 Datasheet - Page 123

• Manufacturer Part Number: lan9303
• Description: Small Form Factor Three Port 10/100 Managed Ethernet Switch With Single Mii/rmii/turbo Mii
• Manufacturer: Standard Microsystems Corp.

Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII
Datasheet
SMSC LAN9303/LAN9303i
9.1.3.2
9.1.3.3
9.1.3.4
9.1.3.5
and a high selects the internal 50MHz clock. The high setting also enables P0_OUTCLK as an output
to be used as the system reference clock.
Clock Drive Strength
When P0_OUTCLK is configured as an output via the
Special Control/Status Register
the setting of the
(VPHY_SPECIAL_CONTROL_STATUS). A low selects 12ma, a high selects 16ma.
Signal Quality Error (SQE) Heartbeat Test
The SQE_HEARTBEAT signal is not generated when operating in RMII PHY mode. The
of the
effect when operating in RMII PHY mode.
Collision Test
External MAC collision testing is not available when operating in the RMII PHY mode. The
Test (VPHY_COL_TEST)
effect on system operation in RMII PHY mode.
Switch Engine collision testing is available and is enabled when the
the
test mode, any transmissions from the Switch Engine will result in the assertion of an internal collision
signal to the Switch Fabric Port 0. Switch Engine collision test occurs regardless of the setting of the
Isolate (VPHY_ISO)
Loopback Mode
Two forms of loopback testing are available: External MAC loopback and Switch Engine loopback.
External MAC loopback is enabled when the
Basic Control Register (VPHY_BASIC_CTRL)
sent to the Switch Engine. Instead, they are looped back onto the receive path. Transmissions from
the Switch Engine are ignored.
Switch Engine loopback is enabled when the
Control/Status Register (VPHY_SPECIAL_CONTROL_STATUS)
Engine are not sent to the external MAC. Instead, they are looped back internally onto the receive
path. Transmissions from the external MAC are ignored. An internal collision signal to the Switch
Engine is available and is asserted when the
loopback occurs regardless of the setting of the
.
Virtual PHY Special Control/Status Register (VPHY_SPECIAL_CONTROL_STATUS)
Virtual PHY Special Control/Status Register (VPHY_SPECIAL_CONTROL_STATUS)
RMII/Turbo MII Clock Strength
bit.
bit of the
(VPHY_SPECIAL_CONTROL_STATUS), its drive strength is based on
DATASHEET
Virtual PHY Basic Control Register (VPHY_BASIC_CTRL)
123
Switch Looopback Port 0
Loopback (VPHY_LOOPBACK)
is set. Transmissions from the external MAC are not
Switch Collision Test Port 0
bit of the
Isolate (VPHY_ISO)
RMII Clock Direction
Virtual PHY Special Control/Status Register
is set. Transmissions from the Switch
Switch Collision Test Port 0
bit.
bit of the
bit is set. Switch Engine
bit of the
bit of the
Revision 1.3 (08-27-09)
Virtual PHY Special
is set. In this
SQEOFF
Virtual PHY
Virtual PHY
Collision
has no
has no
bit of
bit