adm6999g Infineon Technologies Corporation, adm6999g Datasheet - Page 19

• Manufacturer Part Number: adm6999g
• Description: 8 Port 10/100 Mb/s + Gigabit Single Chip Ethernet Switch Controller
• Manufacturer: Infineon Technologies Corporation

3.2.2.4
The de-scrambler acquires synchronization with the data stream by recognizing idle bursts of 40 or more bits and
locking its deciphering Linear Feedback Shift Register (LFSR) to the state of the scrambling LFSR. Upon achieving
synchronization, the incoming data is XORed by the deciphering LFSR and de-scrambled.
In order to maintain synchronization, the de-scrambler continuously monitors the validity of the unscrambled data
that it generates. To ensure this, a link state monitor and a hold timer are used to constantly monitor the
synchronization status. Upon synchronization of the de-scrambler the hold timer starts a 722 us countdown. Upon
detection of sufficient idle symbols within the 722 us period, the hold timer will reset and begin a new countdown.
This monitoring operation will continue indefinitely given a properly operating network connection with good signal
integrity. If the link state monitor does not recognize sufficient unscrambled idle symbols within 722 us period, the
de-scrambler will be forced out of the current state of synchronization and reset in order to re-acquire
synchronization.
3.2.2.5
The symbol alignment circuit in the ADM6999G/GX determines code word alignment by recognizing the /J/K
delimiter pair. This circuit operates on unaligned data from the de-scrambler. Once the /J/K symbol pair (11000
10001) is detected, subsequent data is aligned on a fixed boundary.
3.2.2.6
The symbol decoder functions as a look-up table that translates incoming 5B symbols into 4B nibbles. The symbol
decoder first detects the /J/K symbol pair preceded by idle symbols and replaces the symbol with MAC preamble.
All subsequent 5B symbols are converted to the corresponding 4B nibbles for the duration of the entire packet.
This conversion ceases upon the detection of the /T/R symbol pair denoting the end of stream delimiter (ESD).
The translated data presented on the internal RXD[3:0] signal lines with RXD[0] represents the least significant bit
of the translated nibble.
3.2.2.7
The valid data signal (RXDV) indicates that recovered and decoded nibbles are being presented on the internal
RXD[3:0] synchronous to receive clock, RXCLK. RXDV is asserted when the first nibble of translated /J/K is ready
for transfer over the internal MII. It remains active until either the /T/R delimiter is recognized, link test indicates
failure, or no signal is detected. On any of these conditions, RXDV is de-asserted.
3.2.2.8
The RXER signal is used to communicate receiver error conditions. While the receiver is in a state of holding
RXDV asserted, the RXER will be asserted for each code word that does not map to a valid code-group.
3.2.2.9
The 100Base-X link monitor function allows the receiver to ensure that reliable data is being received. Without
reliable data reception, the link monitor will halt both transmitting and receiving operations until such time that a
valid link is detected.
The ADM6999G/GX performs the link integrity test as outlined in IEEE 100Base-X (Clause 24) link monitor state
diagram. The link status is multiplexed with 10Mbits/s link status to form the reportable link status bit in serial
management register 1
When persistent signal energy is detected on the network, the logic moves into a Link-Ready state after
approximately 500 µs, and waits for an enable from the auto negotiation module. When receiving, the link-up state
is entered, and the transmission and reception logic blocks become active. Should auto negotiation be disabled,
the link integrity logic moves immediately to the link-up state after entering the link-ready state.
Data Sheet
Data De-scrambling
Symbol Alignment
Symbol Decoding
Valid Data Signal
Receive Errors
100Base-X Link Monitor
H
, and driven to the LNKACT pin.
19
Rev 1.31, 2005-11-25
ADM6999G/GX
Descriptions