adm6999g Infineon Technologies Corporation, adm6999g Datasheet - Page 13

• Manufacturer Part Number: adm6999g
• Description: 8 Port 10/100 Mb/s + Gigabit Single Chip Ethernet Switch Controller
• Manufacturer: Infineon Technologies Corporation

Table 3
Pin or Ball
No.
63
61
60
59
55
54
51
50
62
66
Data Sheet
ADM6999G/GX-128 PINS(8 TP + GPSI/RMII)
Name
GTXD0
GFCEN
GTXD1
GTXD2
GTXD3
GTXD4
GTXD5
GTXD6
GTXD7
P7FX
GTXER
PHYAS0
GTXEN
Pin
Type
I/O
I/O
O
I/O
I/O
I/O
I/O
Buffer
Type
8mA, PU Giga Port transmit data 0
8mA, PU Setting GFCEN: Global Flow Control Enable.
8mA
8mA, PD Setting Port7 FX/TX Mode select
8mA, PD Giga Port Transmit Error
8mA, PD Setting PHYAS0: Chip physical address0 for multiple
8mA, PD Giga Port Transmit Enable.
Function
Acts as GMII transmit data TXD0 synchronous to the rising
edge of TXCLK
At power-on-reset, latched as Flow control setting
0
1
Giga Port Transmit Data bit 1~7
Synchronous to the rising edge of GTXCLK
Internal pull down.
0
1
chip application on EEPROM access.
Internal pull down
Power on reset value PHYAS0 combines with
PHYAS1(LEDDATA).
PHYAD Gigabit PHY Address
Master: ADM6999G/GX will read 93C46 EEPROM first
Bank.(00
If there is no EEPROM then user must use 93C66 timing to
write chip's register.
If user put 93C46 with correct Signature then user writes
chip register by 93C46 timing.
If user put 93C66 then data put in Bank0. User can write
chip register by 93C66 timing.
User must assert one SK cycle when CS is at idle stage and
chip internal registers are being writing.
B
B
B
B
13
00
1)2)
, Disable flow-control
, Enable flow-control (default)
, Port7 as TX port
, Port7 as FX port
(cont’d)
H
~27
H
).
08
H
Input and Output Signals
Master
Rev 1.31, 2005-11-25
ADM6999G/GX