mc33696fje/r2 Freescale Semiconductor, Inc, mc33696fje/r2 Datasheet - Page 10

• Manufacturer Part Number: mc33696fje/r2
• Description: Mc33696 Pll Tuned Uhf Transceiver
• Manufacturer: Freescale Semiconductor, Inc

Register Access through SPI
The fractional divider offers high flexibility in the frequency generation for:
Frequencies are controlled by means of registers. To allow for user preference, two programming access
methods are offered (see
11
11.1 SPI Interface
the MC33696 and the MCU communicate via a bidirectional serial digital interface. According to the
selected mode, the MC33696 or the MCU manages the data transfer. The MC33696’s digital interface can
be used as a standard SPI (master/slave) or as a simple interface (SPI deselected). In the latter case, the
interface’s pins are used as standard I/O pins. However, the MCU has the highest priority, as it can control
the MC33696 by setting CONFB pin to the low level.
The interface is operated by four I/O pins.
Table 5
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Switching between transmit and receive modes.
Achieving frequency modulation in FSK modulation transmission.
Performing multi-channel links.
Trimming the RF carrier.
In friendly access, all frequencies are computed internally from the contents of the carrier
frequency and deviation frequency registers.
In direct access, the user programs direct all three frequency registers.
SEB — Serial interface Enable
When SEB is set high, pins SCLK, MOSI, and MISO are set to high impedance. This allows
individual selection in a multiple device system, where all devices are connected via the same bus.
The rest of the circuit remains in the current state, enabling fast recovery times, but the power
amplifier is disabled to prevent any uncontrolled RF transmission.
SCLK — Serial Clock
Synchronizes data movement in and out of the device through its MOSI and MISO lines. The
master and slave devices can exchange a byte of information during a sequence of eight clock
cycles. Since SCLK is generated by the master device, this line is an input on a slave device.
MOSI — Master Output Slave Input
Transmits bytes when master, and receives bytes when slave, with the most significant bit first.
When no data are output, SCLK and MOSI force a low level.
MISO — (Master Input) Slave Output
Transmits data when slave, with the MSB first. There is no master function. Data are valid on
falling edges of SCLK. This means that the clock phase and polarity control bits of the
microcontroller SPI have to be CPOL = 0 and CPHA = 1 (using Freescale acronyms).
summarizes the serial digital interface feature versus the selected mode.
Register Access through SPI
Section 17.3, “Frequency
MC33696 Data Sheet, Rev. 9
Registers”).
Freescale Semiconductor