mc33696fje/r2 Freescale Semiconductor, Inc, mc33696fje/r2 Datasheet
mc33696fje/r2
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mc33696fje/r2 Summary of contents
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... OOK and FSK transmission and reception • 20 kbps maximum data rate using Manchester coding • supply voltage • Programmable via SPI • 6 kHz PLL frequency step © Freescale Semiconductor, Inc., 2006, 2007. All rights reserved. LQFP32 RSSIOUT 1 VCC2RF 2 RFIN 3 GNDLNA 4 ...
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... Transmitter: • 7.25 dBm output power • Programmable output power • FSK done by PLL programming Ordering information Temperature Range –40°C to +85°C –20°C to +85°C 2 QFN Package LQFP Package MC33696FCE/R2 MC33696FJE/R2 MC33696FCAE/R2 MC33696FJAE/R2 MC33696 Data Sheet, Rev. 9 Freescale Semiconductor ...
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Freescale Semiconductor Figure 1. Block Diagram MC33696 Data Sheet, Rev. 9 Features 3 ...
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Pin Functions 3 Pin Functions Pin Name 1 RSSIOUT 2 VCC2RF 3 RFIN 4 GNDLNA 5 VCC2VCO 6 GNDPA1 7 RFOUT 8 GNDPA2 9 XTALIN 10 XTALOUT 11 VCCINOUT 12 VCC2OUT 13 VCCDIG 14 VCCDIG2 15 RBGAP 16 GND 17 ...
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Silicon Version This data sheet describes the functional features of silicon version ES4.1. 5 Maximum Ratings Parameter Supply voltage on pin: VCCIN Supply voltage on pins: VCCINOUT, VCCDIG Supply voltage on pins: VCC2IN, VCC2RF, VCC2VCO Voltage allowed on each ...
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Power Supply 6 Power Supply Table 3. Supply Voltage Range Versus Ambient Temperature Parameter Supply voltage on VCCIN, VCCINOUT, VCCDIG for 3 V operation Supply voltage on VCCIN for 5 V operation Supply voltage on VCCPA for ...
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VCC2 1 RSSIOUT 2 VCC2RF VCC2 3 RFIN 4 GNDLNA U11 5 MC33696 VCC2VCO VCC2 6 GNDPA1 7 RFOUT 8 GNDPA2 VCC2 3V Operation A second voltage regulator supplies the digital part. This regulator is powered from pin VCCDIG and ...
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Transmitter Functional Description injection I/Q mixer driven by the frequency synthesizer. An integrated poly-phase filter performs rejection of the image frequency. The low intermediate frequency allows integration of the IF filter providing the selectivity. The center frequency is tuned by ...
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Frequency Planning 10.1 Clock Generator All clocks running in the circuit are derived from the reference frequency provided by the crystal oscillator (frequency f , period t ). The crystal frequency is chosen in relation to the band in ...
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Register Access through SPI The fractional divider offers high flexibility in the frequency generation for: • Switching between transmit and receive modes. • Achieving frequency modulation in FSK modulation transmission. • Performing multi-channel links. • Trimming the RF carrier. Frequencies ...
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Table 5. Serial Digital Interface Feature versus Selected Mode (SEB = 1) Selected Mode Configuration SPI slave, data received on MOSI, SCLK from MCU, MISO is output Transmit SPI deselected, MOSI receives encoded data from MCU Receive DME = 1 ...
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Register Access through SPI Figure 4 and Figure 5 show write and read operations in a typical SPI transfer. In both cases, the SPI is a slave. A received byte is considered internally on the eighth falling edge of SCLK. ...
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Bit Definition Two sets of configuration registers are available. They are grouped in two different banks: Bank A and Bank B. Two bits are used to define which bank represents the state of the component. Bit Name Direction BANKA ...
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CONFIG1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit Name LOF1 LOF0 CF1 CF0 RESET Reset Value R/W R/W R/W R/W R 304–434 304–315 315–434 314 No ...
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FT1-A 700701 h Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit Name FTA11 FTA10 FTA9 FTA8 FTA7 Reset Value R/W R/W R/W R/W R/W 07h FT2 Bit 7 Bit ...
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Register Access through SPI 11.3.3 Direct Switch Control The conditions to enter direct switch control are: • Strobe pin = V CC • SOE bit = 0 By simply writing BANKA and BANKB, the active bank will be defined: BANKA ...
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BANKA = 0, BANKB = 1 State B OFF Strobe Pin If strobe pin is 1, configuration is defined by Bank B, BANKS = 0. If strobe pin is 0, MC33696 configuration is OFF message is received ...
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Register Access through SPI 11.3.5.1 BANKA = X, BANKB = 0 State A OFF If strobe pin is 1, configuration is defined by Bank A, BANKS = 1. If strobe pin is 0, MC33696 configuration is OFF message ...
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If strobe pin is 0 the state is OFF. • If strobe pin is released from 0 while state is OFF, the initial OFF period is completed. • Whenever is the change of duration of one state due to ...
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Communication Protocol • ID: The ID allows selection of the correct device transmission, as the content has been loaded previously in the ID register. Its length is variable, defined by the IDL[1:0] bits. The complement of the ...
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It is possible to build a tone to form the detection sequence by programming the ID register with a full sequence of ones or zeroes. In this case, the header (or its complement) must not be found in this tone ...
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Data Manager Receiver Off On Status RF Signal 13 Data Manager In receive mode, Manchester coded data can be processed internally by the data manager. After decoding, the data are output on the digital interface, in SPI format. This minimizes ...
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Each time is defined with the associated value found in the RXONOFF register. • On time = RON[3:0] x 512 x T • Off time = receiver OFF time = from ROFF[2:0] (see Table The strobe oscillator ...
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Received Signal Strength Indicator (RSSI) In OOK modulation (MODU=0), modulation is performed by switching on and off the RF output stage. MOSI = 0: output stage off MOSI = 1: output stage on In FSK modulation (MODU = 1), modulation ...
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At the LNA output, the LNA AGC control voltage is used to monitor input signals in the range –50 dBm to –20 dBm. Therefore, the logarithmic amplifier provides information relative to the in-band signal, whereas the LNA AGC voltage ...
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Received Signal Strength Indicator (RSSI) 16.2 Operation Two modes of operation are available: sample mode and continuous mode. 16.2.1 Sample Mode Sample mode allows the peak power of a specific pulse in an incoming frame to be measured. The quasi ...
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Continuous Mode Continuous mode is used to make a peak measurement on an incoming frame, without having to select a specific pulse to be measured. The quasi peak detector is reset by closing S1. After ...
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Configuration, Command, and Status Registers 17.1 Configuration Registers Figure 19 describes configuration register 1, CONFIG1. Bit 7 Bit 6 Bit Name LOF1 LOF0 Reset Value 1 0 Table 9. LOF[1:0] and CF[1:0] Setting Versus Carrier Frequency Carrier Frequency 304 MHz ...
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Figure 20 describes configuration register 2, CONFIG2. Bit 7 Bit 6 Bit Name DSREF FRM Reset Value 0 0 DSREF (Data Slicer Reference) selects the data slicer reference Fixed reference (cannot be used in FSK Adaptive ...
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Configuration, Command, and Status Registers SOE (Strobe Oscillator Enable) enables the strobe oscillator disabled 1 = enabled Figure 21 describes configuration register 3, CONFIG3. Bit 7 Bit 6 Bit Name AFF1 AFF0 Reset Value 0 0 OLS (Out ...
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AFF1 If AFFC is reset, the average filter frequency is directly defined by bits DR[1:0], as shown in If AFFC is set, AFF[1:0] allow the overall receiver sensitivity to be improved by reducing the average filter cut-off frequency. The typical ...
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Configuration, Command, and Status Registers 0 = Receive mode 1 = Transmit mode RSSIE (RSSI Enable) enables the RSSI function Disabled 1 = Enabled EDD (Envelop Detector Decay) controls the envelop detector decay Slow decay for ...
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Bit 23 Bit 22 Bit Name FTA11 FTA10 Reset Value 0 1 Bit 15 Bit 14 Bit Name FTA3 FTA2 Reset Value 0 0 Bit 7 Bit 6 Bit Name FTB7 FTB6 Reset Value 0 0 How these registers are ...
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Configuration, Command, and Status Registers FRM = 1 (Direct Access) Whatever type of modulation is used (OOK or FSK), F[11:0] defines the receiver local oscillator frequency F , and, LO • if OOK modulation is used (MODU = 0): — ...
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RON[3:0] ROFF[2:0] (Receiver Off) define the receiver off time as described in Control.” ROFF[2:0] 17.5 ID and Header Registers Figure 26 defines the ID register, ID. Bit 7 Bit 6 Bit Name IDL1 IDL0 Reset Value 1 1 IDL[1:0] (Identifier ...
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Controller Bit 7 Bit 6 Bit Name HDL1 HDL0 Reset Value 1 0 HDL[1:0] (Header Length) sets the length of the header, as shown on HD[5:0] (Header) sets the header. The header is Manchester coded. Its LSB corresponds to the ...
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External signal and internal conditions: see enter standby/LVD mode. After a POR, the circuit is in state 60 (see value. At any time, a low level applied to CONFB forces the finite state machine into state 1, whatever the ...
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Controller STROBE SPI Startup Time CONFB SEB Figure 31. Second Valid Sequence from Standby/LVD Mode to Configuration Mode 18.2 Transmit Mode In transmit mode, the state diagram is reduced to only one state: state 30. The circuit is either waiting ...
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State 0: The receiver is off, but the strobe oscillator and the off counter are running. Forcing the STROBE pin low maintains the system in this state. State 0b: The receiver is kept on by the STROBE pin or the ...
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Controller State 13: A header, or its complement, has been received. Data and clock signals are output on the SPI port until EOM indicates the end of the data sequence. If the complement of the header has been received, output ...
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Data Manager Enabled and Strobe Pin Control Figure 35 shows the state diagram when the data manager is enabled and the strobe oscillator is disabled. In this configuration, the receiver is controlled only externally by the MCU. SPI Master ...
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Controller output data are complemented also. When an EOM occurs before the current byte is fully shifted out, dummy bits are inserted until the number of shifted bits is a multiple of 8. For all states: At any time, a ...
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Electrical Characteristics 19.1 General Parameters Operating supply voltage and temperature range see schematic (see Figure 47), unless otherwise specified. Typical values reflect average measurement at V Parameter 1.2 Supply current in receive mode 1.3 1.4 Supply current in transmit ...
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Electrical Characteristics Operating supply voltage and temperature range see schematic (see Figure 47), unless otherwise specified. Typical values reflect average measurement at V Parameter 2.41 OOK sensitivity at 868 MHz DME = 1, DSREF = 4.8 kbps, ...
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Operating supply voltage and temperature range see schematic (see Figure 47), unless otherwise specified. Typical values reflect average measurement at V Parameter 2.18 Image frequency rejection 304–434 MHz 2.19 868–915 MHz 1.4 1.2 1 0.8 0.6 0.4 0.2 0 -0.2 ...
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Electrical Characteristics 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 2.1 V Figure 37. OOK Sensitivity Variation Versus Voltage 1.4 1.2 1 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -40°C Figure 38. FSK Sensitivity Variation Versus Temperature 46 OOK ...
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V Figure 39. FSK Sensitivity Variation Versus Voltage 2400 Figure 40. OOK Sensitivity Variation Versus Data Rate Freescale Semiconductor FSK Sensitivity Variation ...
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Electrical Characteristics 2400 Figure 41. FSK Sensitivity Variation Versus Data Rate (Ref : 25°C, 3V, 434MHz, FSK +/-64kHz, 4800bps ...
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Receiver Parameters Operating supply voltage and temperature range see schematic (see Figure 47), unless otherwise specified. Typical values reflect average measurement at V Parameter Receiver: IF filter, IF Amplifier, FM-to-AM Converter and Envelope Detector 3.1 IF center frequency 3.2 ...
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Electrical Characteristics Operating supply voltage and temperature range see schematic (see Figure 47), unless otherwise specified. Typical values reflect average measurement at V Parameter 4.1 Output power at 315 MHz 4.16 Output power at 434 MHz 4.2 Output power at ...
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Operating supply voltage and temperature range see schematic (see Figure 47), unless otherwise specified. Typical values reflect average measurement at V Parameter 4.81 RFOUT optimum load resistance at 434 MHz 4.82 RFOUT optimum load resistance at 868 MHz 4.83 RFOUT ...
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Electrical Characteristics 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 2.1 V Figure 44. Output Power Versus Supply Voltage 19.5 PLL & Crystal Oscillator Operating supply voltage and temperature range see schematic (see Figure 47), unless otherwise specified. Typical values ...
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Strobe Oscillator (SOE = 1) Operating supply voltage and temperature range see schematic (see Figure 47), unless otherwise specified. Typical values reflect average measurement at V Parameter 6.1 Period range 6.2 External capacitor C3 6.3 Sourced/sink current 6.4 High ...
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Electrical Characteristics 19.8 Digital Output Operating supply voltage and temperature range see schematic (see Figure 47), unless otherwise specified. Typical values reflect average measurement at V Parameter 8.1 Output low voltage 8.2 Output high voltage 8.3 Fall and rise time ...
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SEB 9.8 CONFB 9.3 SCLK (input) 9.2 9.10 MOSI (input) 9.7 MISO (output) Figure 45. Digital Interface Timing Diagram in Configuration Mode SEB CONFB 9.3 SCLK (input) 9.6 MOSI (output) Figure 46. Digital Interface Timing Diagram in Receive Mode (DME ...
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Application Schematics 20 Application Schematics VCCINOUT C28 L10 J1 SMA Vert C36 L7 C39 C40 Figure 47. MC33696 Application Schematic (5 V) 20.1 PCB Design Recommendations Pay attention to the following points and recommendations when designing the layout of the ...
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Power Supply, Ground Connection and Decoupling — Connect each ground pin to the ground plane using a separate via for each signal; do not use common vias. — Place each decoupling capacitor as close to the corresponding ...
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Case Outline Dimensions 21 Case Outline Dimensions 21.1 LQFP32 Case 58 MC33696 Data Sheet, Rev. 9 Freescale Semiconductor ...
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Freescale Semiconductor MC33696 Data Sheet, Rev. 9 Case Outline Dimensions 59 ...
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Case Outline Dimensions 60 MC33696 Data Sheet, Rev. 9 Freescale Semiconductor ...
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QFN32 Case Freescale Semiconductor MC33696 Data Sheet, Rev. 9 Case Outline Dimensions 61 ...
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Case Outline Dimensions 62 MC33696 Data Sheet, Rev. 9 Freescale Semiconductor ...
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Freescale Semiconductor MC33696 Data Sheet, Rev. 9 Case Outline Dimensions 63 ...
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... Freescale Semiconductor was negligent regarding the design or manufacture of the part. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2006, 2007. All rights reserved. ...