adav804 Analog Devices, Inc., adav804 Datasheet
adav804
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adav804 Summary of contents
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... DVD-Recordable All Formats CD-R/W PRODUCT OVERVIEW The ADAV804 is a stereo audio codec intended for applications, such as DVD or CD recorders, requiring high performance, flexible and cost effective playback and record functionality. The ADAV804 features Analog Devices proprietary, high performance converter cores to provide record (ADC), playback (DAC) and format conversion (SRC single chip ...
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... ADAV804 TABLE OF CONTENTS Specifications..................................................................................... 3 Timing Specifications....................................................................... 7 Absolute Maximum Ratings............................................................ 8 ESD Caution.................................................................................. 8 Pin Configuration and Function Descriptions............................. 9 Functional Description .................................................................. 12 ADC Section ............................................................................... 12 DAC Section.................................................................................... 15 SRC Functional Overview ............................................................. 16 Theory of Operation .................................................................. 16 REVISION HISTORY Preliminary Technical Data Conceptual High Interpolation Model.................................... 16 Hardware Model......................................................................... 17 The Sample Rate Converter Architecture ............................... 17 PLL Section ...
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... Min Typ Max 100 99 102 −85 1.0 1.5 −1 0.01 100 TBD 100 0.39 -48 TBD Rev Page ADAV804 +3.3 V +3.3 V 25°C 12.288 MHz kHz 24-bits 100 pF 997Hz at −1 dBFS 997Hz at −1 dBFS Unit Conditions kΩ Unit Conditions V ° ppm/ ...
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... ADAV804 Table 5. ADC Low-Pass Digital Decmation Filter Characteristics Sample Rate Pass Band (kHz) Frequency (kHz) 48 0.45314 × TBD × Guaranteed by Design Table 6. ADC High-Pass Digital Filter Characteristics (f Cutoff Frequency Table 7. SRC Section Resolution Sample Rate Maximum Sample Rate Ratios ...
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... TBD TBD TBD Min Typ Max 27.2 220 Min Typ Max 2.0 DVDD 0 2.4 0.4 15 Rev Page ADAV804 Pass Band Ripple (dB) ±0.002 ±0.002 ±0.005 Unit Conditions MHz MHz × f 256/384/512/768 × 32/44.1/48 kHz × f 256/384/512/768 × 32/44.1/48 kHz × f 256/512 × ...
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... ADAV804 Table 14. Power Supplies Voltage, AVDD Voltage, DVDD Voltage, ODVDD Analog Current Digital Current, DVDD Digital Interface Current, ODVDD Analog Current—Power Down Digital Current - Power Down Digital Interface Current - Power Down Power Supply Rejection 1 kHz 300 mV Signal at Analog Supply Pins ...
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... Min Typ 25 −40 −65 Rev Page ADAV804 Comments Relevant for Repeated Start Condition After this period the 1st clock is generated To xBCLK Rising Edge From xBCLK Rising Edge To xBCLK Rising Edge From xBCLK Rising Edge From xBCLK Falling Edge ...
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... ADAV804 ABSOLUTE MAXIMUM RATINGS Table 17. Parameter Rating DVDD to DGND and ODVDD 4 DGND AVDD to AGND 4.6 V Digital Inputs DGND − 0 DVDD + 0.3 V Analog Inputs AGND − 0 AVDD + 0.3 V AGND to DGND −0 +0.3 V Reference Voltage Indefinite short circuit to ground Soldering (10 s) +300° ...
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... Preliminary Technical Data PIN CONFIGURATION AND FUNCTION DESCRIPTIONS DIR_GND DIR_VDD ZEROL/INT Table 18. ADAV804 Pin Function Descriptions Pin Number Input/Output Mnemonic 1 INPUT VINR 2 INPUT VINL 3 AGND 4 AVDD 5 DIR_LF 6 DIR_GND 7 DIR_VDD 8 INPUT RESET 9 INPUT AD0 10 INPUT/OUTPUT SDA 11 INPUT SCL 12 INPUT AD1 13 OUTPUT ZEROL/INT ...
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... ADAV804 Pin Number Input/Output Mnemonic 23 INPUT DIRIN 24 ODVDD 25 ODGND 26 OUTPUT DITOUT 27 INPUT/OUTPUT OAUXLRCLK 28 INPUT/OUTPUT OAUXBCLK 29 OUTPUT OAUXSDATA 30 INPUT/OUTPUT IAUXLRCLK 31 INPUT/OUTPUT IAUXBCLK 32 INPUT IAUXSDATA 33 DGND 34 DVDD 35 INPUT MCLKI 36 OUTPUT MCLKO 37 INPUT XOUT 38 INPUT XIN 39 OUTPUT SYSCLK3 40 OUTPUT SYSCLK2 41 OUTPUT SYSCLK1 42 DGND 43 PLL_VDD ...
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... Preliminary Technical Data (continued from Page 1) Operation of the ADAV804 is controlled via an I interface, which allows individual Control Register settings to be programmed. The ADAV804 operates from a single analog +3.3 V power supply - and a digital power supply of +3.3 V with optional digital interface range housed in ...
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... ADAV804 FUNCTIONAL DESCRIPTION ADC SECTION The ADAV804's ADC section is implemented using a 2 multi-bit (5-bits) Sigma-Delta modulator. The modulator is sampled at either half the ADC MCLK rate (Modulator Clock = 128 × quarter of the ADC MCLK rate (Modulator Clock × The digital decimator consists of a Sinc^5 filter S followed by a cascade of 3 half-band FIR filters ...
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... Attack and Recovery thresholds to prevent excessive volume modulation caused by continuous gain adjustments. Limited Recovery Limited Recovery Mode offers a compromise between No Recovery and Normal Recovery Modes. If the output level of the ADC exceeds the Attack Threshold then Attack Mode is Rev Page ADAV804 ...
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... ADAV804 initiated. When Attack Mode has reduced the PGA gain to suitable levels the ALC will attempt to recovery the gain to its original level. If the ADC output level exceeds the level set by the Recovery Threshold bits a counter is incremented (GAINCNTR). This counter is incremented, at intervals equal ...
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... Preliminary Technical Data DAC SECTION The ADAV804 has two DAC channels arranged as a stereo pair with differential outputs. Each channel has its own independently programmable attenuator, adjustable in 128 steps of 0.375dB per step. The DAC can receive data from the playback or auxiliary input ports, the SRC, the ADC or the DIR. ...
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... Since the ratio irrational number, the error resulting from the re- sampling at fS_OUT can never be eliminated. However, the error can be significantly reduced through interpolation of the input data at fS_IN. The sample rate converter in the ADAV804/ is conceptually interpolated by a factor of 2 ZERO-ORDER IN ...
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... SERVO LOOP SAMPLE RATE RATIO FIR FILTER f S_IN SAMPLE RATE RATIO f S_OUT EXTERNAL RATIO Figure 12. Architecture of the Sample Rate Converter /f ) when f < The FIFO also scales the input S_IN S_OUT S_IN ADAV804 sample rates HIGH ORDER INTERP L/R DATA OUT 801-0011 S_IN ...
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... The FIR S_IN S_OUT Figure 14. Frequency Response of the Digital Servo Loop. fS_IN is the X-Axis, period. The FIR S_OUT PLL SECTION The ADAV804 features a dual PLL configuration to generate for f ≥ independent system clocks for asynchronous operation. Figure S_OUT S_OUT 17 shows the block diagram of the PLL section. The PLL generates the internal and system clocks from a 27MHz clock ...
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... PLL1 and PLL2 are selected. The clock nodes, PLL1 and PLL2, can be used as master clocks for the other blocks in the ADAV804 such as the DAC or ADC. The PLL has separate supply and ground pins and these should be as clean as possible to prevent electrical noise being converted into clock jitter by coupling onto the loop filter pins ...
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... ADAV804. Additionally the clock source for the SPDIF transmitter can be selected from the various clock sources available in the ADAV804. The receiver uses two pins, DIRIN and DIR_LF. DIRIN accepts the SPDIF input data stream. The DIRIN pin can be configured to accept a digital ...
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... DIR_LF Figure 22. DIR loop Filter Components Serial Digital Audio Transmission Standards The ADAV804 can receive and transmit SPDIF, AES/EBU and IEC-958 serial streams. SPDIF is a consumer audio standard and AES/EBU is a professional audio standard. IEC-958 has both consumer and professional definitions. This data sheet is ...
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... Receiver Section The ADAV804 uses a double buffering scheme to handle Non- Pro/Con Audio =1 reading Channel Status and User bit information. The Channel Channel Mode ...
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... BCONF3 bit. If the bit is 0 the user bits will begin transmitting straight away without alignment to the Z preamble. If this bit is 1 the User bits will not start transmitting until a Z preamble occurs when the TxBCONF2-1 bits are 01. Rev Page ADAV804 DITOUT CHANNEL STATUS A ( BITS) ...
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... Autobuffer register enables zeros to be added or subtracted between messages. Interrupts SPDIF OUT The ADAV804 provides interrupt bits to indicate the presence of certain conditions which may require attention. Reading the Interrupt Status register will allow the user to determine if any 0.....7 of the interrupts have be asserted. The bits of the Interrupt 8 ...
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... BCLK MSB SDATA CLOCKING SCHEME The ADAV804 provides a flexible choice of on-chip and off- chip clocking sources. The on-chip oscillator with dual-PLLs is intended to offer complete system clocking requirements for use with available MPEG encoders, decoders or combination codecs. The oscillator function is designed for generation MHz video clock from a 27 MHz crystal connected between XIN and XOUT pins ...
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... R/W bit. The device address consists of an internal built-in address (0b00100) and two address pins, AD1 and AD0. The two address pins allow up to four ADAV804s to be used in a system. Initiating a write operation to the ADAV804 involves sending a START condition and then sending the device address with the R/W set low ...
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... ADAV804. Finally the user can send another frame with the 8 data bits required to be written to the register. A third ACK is issued by the ADAV804 after which the user can send a STOP condition to complete the data transfer. A read operation requires that the user first write to the ADAV804 to point to the correct register and then read the data ...
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... ADAV804 data buffers. Using a block read or write to access these registers will not update the absolute register address but rather will Preliminary Technical Data update the buffer address to provide the next value in the buffer. Rev Page ...
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... Selects the source for SPDIF Output (DITOUT) TxMUX 0 = SPDIF Transmitter - Normal Mode 1 = DIRIN - Loopback Mode CLK2- CLK2- SRCDIV DIV1 DIV0 RES RES RES Rev Page ADAV804 CLK1- CLK1- MCLK- MCLK- DIV1 DIV0 SEL1 SEL0 RES RES RES TxMUX ...
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... ADAV804 Table 28. Playback Port Control Register RES 7 ADDRESS = 0000100 CLKSRC1-0 Selects the Clock Source for generating the ILRCLK and IBCLK 00 = Input Port is a Slave 01 = Recovered PLL Clock 10 = Internal Clock Internal Clock 2 SPMODE1-0 Selects the serial format of the Playback Port 000 = Left Justified ...
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... Bits Bits SPMODE1-0 Selects the serial format of the Auxiliary Record Port 00 = Left Justified Reserved 11 = Right Justified CLKSRC1 CLKSRC0 WLEN1 CLKSRC1 CLKSRC0 WLEN1 Rev Page ADAV804 WLEN0 SPMODE1 SPMODE0 WLEN0 SPMODE1 SPMODE0 ...
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... ADAV804 Table 32. Group Delay and Mute Register ADDRESS = 0001000 MUTE_SRC GRPDLY6-0 Table 33. Receiver Configuration 1 Register NO- CLOCK 7 ADDRESS = 0001001 NOCLOCK Selects the source of the Receiver Clock when the PLL is not locked 0 = The Recovered PLL Clock is used 1 = ICLK1 is used Determines the oversampling ratio of the Recovered Receiver Clock RXCLK1 RxCLK is a 128 × ...
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... Bits with Preamble-Z as the start of the buffer 1 = 768 Bits with Preamble-Z as the start of the buffer SP_PLL_ SP-PLL SEL1-0 6 5,4 RES RES RxBCONF5 RxBCONF4 Rev Page NON- RES RES AUDIO RxBCONF3 RxBCONF2-1 3 2,1 ADAV804 NO_ VALIDITY 0 RxBCONF0 0 ...
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... ADAV804 Table 36. Transmitter Control Register RES Tx-VALIDITY 7 6 ADDRESS = 0001100 TxVALIDITY This bit is used to set or clear the VALIDITY bit in the AES3/SPDIF Transmit stream 0 = Audio is suitable for D/A conversion 1 = Audio is not suitable for D/A conversion Determines the AES3/SPDIF Transmit to AES3/SPDIF Receiver ratio TxRATIO2-0 000 = Transmitter to Receiver Ratio is 1:1 ...
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... Table 40. Transmitter Message Zeros Least Significant Byte LSBZeros7-0 7,6,5,4,3,2,1,0 ADDRESS = 0010000 LSBZero7-0 The least significant byte of the number of zeros to be stuffed between IEC60958-3 messages (packets) Default = 0x09 Tx_A/B Disable_ Same Tx_Copy RES Rev Page ADAV804 RES TxCSSWITCH RxCSSWITCH ...
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... ADAV804 Table 41. Autobuffer Register RES 7 ADDRESS = 0010001 Zero_Stuff_IU Enables the addition or subtraction of zeros between IUs during autobuffering of the user bits in IEC60958-3 format Zeros added or subtracted 1 = Zeros can be added or subtracted between IUs Auto_UBits Enables the User Bits to be autobuffered between the AES3/SPDIF receiver and ...
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... This bit will be set if the PLL has locked or cleared when the PLL loses lock. Once read it will remain in its state and not generate an interrupt unless it has changed state. Non- NonAudio Emphasis Audio Preamble Rev Page ADAV804 CRC- No- BiPhase/ Error Stream Parity Lock ...
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... ADAV804 Table 49. Receiver Error Mask Register RxValidity Mask 7 ADDRESS = 0011001 Masks the RxValidity bit from generating an interrupt RxValidity Mask 0= The RxValidity bit will not generate an interrupt 1 = The RxVvalidity bit will generate and interrupt Masks the Emphasis bit from generating an interrupt Emphasis Mask ...
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... Error register. This bit will remain high until the Interrupt Status register is read. RES RES RES OVRL Mask TxUB- TxCS- RxCS- INT INT DIFF Rev Page ADAV804 OVRR Mask MUTE_IND MASK 1 0 RxUB- RxCS- Rx- INT BINT ERROR ...
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... ADAV804 Table 53. Interrupt Status Mask Register SRCError Mask 7 ADDRESS = 0011101 SRCError Mask Masks the SRCError bit from generating an interrupt 0 = The SRCError bit will not generate an interrupt 1 = The SRCError bit will generate and interrupt Masks the TxCSTBINT bit from generating an interrupt TxCSTINT Mask ...
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... Non Audio Non Audio RES RES Preamble Frame RCSB7 RCSB6 RCSB5 RCSB4 TCSB6 TCSB5 TCSB4 Rev Page ADAV804 Non Audio Non Audio Subframe_A Subframe_B 1 0 RCSB3 RCSB2 RCSB1 TCSB3 TCSB2 TCSB1 RCSB0 0 TCSB0 0 ...
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... ADAV804 Table 61. Transmitter User Bit Buffer Data Register TxUBDATA07-TxUBDATA00 7,6,5,4,3,2,1,0 ADDRESS = 1010011 TxUBDATA07-00 A write to this register will write 8 bits of user data to the Transmit User bit buffer pointed to by TxUBADDR7-0. When User Bit autobuffering is enabled this buffer is disabled. Table 62. Q Subcode CRC Error Status Register (Read Only) ...
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... SRC Datapath Source Select for DIT DIT2-0 000 = ADC 001 = DIR 010 = Playback 011 = Auxiliary In 100 = SRC SRC0 REC2 REC1 RES DAC2 DAC1 Rev Page ADAV804 REC0 AUXO2 AUXO1 DAC0 DIT2 DIT1 AUXO0 0 DIT0 0 ...
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... ADAV804 Table 66. DAC Control Register 1 DR_ALL 7 ADDRESS = 1100100 DR_ALL Hard Reset and Powerdown 0 = Normal, Output pins Hard Reset & Low Power, Output pins go to AGND DR_ALL DAC Digital Reset 0 = Normal 1 = Reset All except registers CHSEL1-0 DAC Channel Select 00 = Normal Left-Right ...
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... RES RES INTRPT ZEROSEL1 6 5 DVOLL6 DVOLL5 DVOLL4 DVOLR6 DVOLR5 DVOLR4 Rev Page ZFVOL ZFDATA ZFPOL ZEROSEL0 RES RES RES DVOLL3 DVOLL2 DVOLL1 DVOLR3 DVOLR2 DVOLR1 ADAV804 RES 0 DVOLL0 0 DVOLR0 0 ...
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... ADAV804 Table 72. DAC Left Peak Volume Register RES 7 ADDRESS = 1101010 DLP5-0 DAC Left Channel Peak Volume Detection 000000 = 0dBFS 000001 = -1dBFS 111111 = -63dBFS Table 73. DAC Right Peak Volume Register RES 7 ADDRESS = 1101011 DRP5-0 DAC Right Channel Peak Volume Detection 000000 = 0dBFS ...
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... HPF PWRDWN AND_PD RES BUF_PD RES AVOLL5 AVOLL4 AVOLL3 Rev Page ADAV804 MUTER MUTEL PLPD RES MCD1 MCD0 AVOLL2 AVOLL1 AVOLL0 PRPD 0 ...
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... ADAV804 Table 79. ADC Right Volume Register AVOLR7 AVOLR6 7 6 ADDRESS = 1110001 AVOLR7-0 ADC Right Channel Volume Control 1111111 = 1.0 (0dBFS) 1111110 = 0.996 (-0.00348dBFS) 1000000 = 0.5 (-6dBFS) 0111111 = 0.496 (-6.09dBFS) 0000000 = 0.0039 (-48.18dBFS) Table 80. ADC Left Peak Volume Register RES RES 7 6 ADDRESS = 1110010 ...
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... Sample Rate Select for PLL1 FS1 kHz 01 = Reserved kHz 11 = 44.1 kHz Oversample Ratio Select for PLL1 SEL1 0 = 256 × 384 × DOUB1 Double Selected Sample Rate on PLL1 0 = Disabled 1 = Enabled SEL2 DOUB2 FS1 Rev Page ADAV804 FS1-0 SEL1 DOUB1 ...
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... ADAV804 Table 84 .Internal Clocking Control Register 1 DCLK2 7 ADDRESS = 1110110 DCLK2-0 DAC Clock Source Select 000 = XIN 001 = MCLKI 010 = PLLINT1 011 = PLLINT2 100 = DIR PLL (512 × 101 = DIR PLL (256 × 110 = XIN 111 = XIN ACLK2-0 ADC Clock Source Select ...
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... Enables the SYSCLK2 Output 0 = Enabled 1 = Disabled SYSCLK3 Enables the SYSCLK3 Output 0 = Enabled 1 = Disabled RES ICLK1-1 ICLK1 RES RES RES RES DIRIN_PIN RES Rev Page ADAV804 PLL2INT1 PLL2INT0 PLL1INT RES RES RES SYSCLK1 SYSCLK2 SYSCLK3 ...
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... ADAV804 Table 88. ALC Control Register 1 FSSEL1-0 7,6 ADDRESS = 1111011 FSSEL1-0 These bits should equal the sample rate of the ADC kHz kHz kHz 11 = Reserved GAINCNTR1-0 These bits determine the limit of the counter used in Limited Recovery Mode ...
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... Table 90. ALC Control Register 3 ALC RESET 7,6,5,4,3,2,1,0 ADDRESS = 1111101 Default = 0x00 ALC RESET A write to this register will restart the ALC operation. The value written to this register is irrelevant. A read from this register will give the gain reduction factor. Rev Page ADAV804 ...
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... ADAV804 OUTLINE DIMENSIONS ORDERING GUIDE Model Temperature Range ADAV804AST −40°C to +85°C © 2003 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR04755-0-3/04(PrG) Figure 40. 64-Lead Plastic Quad Flatpack [LQFP] (ST-64) Dimensions shown in inches and (millimeters) ...