dp83846a National Semiconductor Corporation, dp83846a Datasheet - Page 9

• Manufacturer Part Number: dp83846a
• Description: Dsphyter ? Single 10/100 Ethernet Transceiver
• Manufacturer: National Semiconductor Corporation

1.7 Reset
1.8 Power and Ground Pins
RX_ER/PAUSE_EN
CRS/LED_CFG
RESET
TTL/CMOS INPUT/OUTPUT SUPPLY
IO_VDD
IO_GND
INTERNAL SUPPLY PAIRS
CORE_VDD
CORE_GND
ANALOG SUPPLY PINS
ANA_VDD
ANA_GND
SUBSTRATE GROUND
SUB_GND
Signal Name
Signal Name
Signal Name
S, O, PU
S, O
PU
35, 43, 57, 65
34, 42, 53, 56, 64
24, 49, 72
23, 48, 73
4, 7, 12, 14
I
2, 6, 9, 13, 15, 18,
19, 76, 79
Type
Type
,
Pin #
46
62
61
Pin #
Pin #
9
PAUSE ENABLE: This strapping option allows advertise-
ment of whether or not the DTE(MAC) has implemented
both the optional MAC control sublayer and the pause func-
tion as specified in clause 31 and annex 31B of the IEEE
802.3x specification (Full Duplex Flow Control).
When left floating the Auto-Negotiation Advertisement Reg-
ister will be set to 0, indicating that Full Duplex Flow Control
is not supported.
When tied low through a 5 k
tisement Register will be set to 1, indicating that Full Duplex
Flow Control is supported.
The float/pull-down status of this pin is latched into the Auto-
Negotiation Advertisement Register during Hardware-Re-
set.
LED CONFIGURATION: This strapping option defines the
polarity and function of the FDPLX LED pin.
See Section 2.3 for further descriptions of this strapping op-
tion.
RESET: Active Low input that initializes or re-initializes the
DP83846A. Asserting this pin low for at least 160 s will
force a reset process to occur which will result in all internal
registers re-initializing to their default states as specified for
each bit in the Register Block section and all strapping op-
tions are re-initialized.
I/O Supply
I/O Ground
Digital Core Supply
Digital Core Ground
Analog Supply
Analog Ground
Bandgap Substrate connection
Description
Description
Description
the Auto-Negotiation Adver-
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