dp83846a National Semiconductor Corporation, dp83846a Datasheet - Page 5

• Manufacturer Part Number: dp83846a
• Description: Dsphyter ? Single 10/100 Ethernet Transceiver
• Manufacturer: National Semiconductor Corporation

1.0 Pin Descriptions
The DP83846A pins are classified into the following inter-
face categories (each interface is described in the sections
that follow):
— MII Interface
— 10/100 Mb/s PMD Interface
— Clock Interface
— Special Connect Pins
— LED Interface
— Strapping Options/Dual Function pins
— Reset
— Power and Ground pins
Note: Strapping pin option (BOLD) Please see Section 1.6
for strap definitions.
1.1 MII Interface
MDC
MDIO
CRS/LED_CFG
COL
TX_CLK
TXD[3]
TXD[2]
TXD[1]
TXD[0]]
TX_EN
TX_ER
Signal Name
I
I/O, OD
O, S
O
O
I
I
I
Type
37
36
61
60
51
59, 58, 55,
54
52
50
Pin #
5
Description
MANAGEMENT DATA CLOCK: Synchronous clock to the
MDIO management data input/output serial interface which
may be asynchronous to transmit and receive clocks. The
maximum clock rate is 25 MHz with no minimum clock rate.
MANAGEMENT DATA I/O: Bi-directional management in-
struction/data signal that may be sourced by the station
management entity or the PHY. This pin requires a 1.5 k
pullup resistor.
CARRIER SENSE: Asserted high to indicate the presence
of carrier due to receive or transmit activity in 10BASE-T or
100BASE-TX Half Duplex Modes, while in full duplex mode
carrier sense is asserted to indicate the presence of carrier
due only to receive activity.
COLLISION DETECT: Asserted high to indicate detection
of a collision condition (simultaneous transmit and receive
activity) in 10 Mb/s and 100 Mb/s Half Duplex Modes.
While in 10BASE-T Half Duplex mode with Heartbeat en-
abled this pin are also asserted for a duration of approxi-
mately 1 s at the end of transmission to indicate heartbeat
(SQE test).
In Full Duplex Mode, for 10 Mb/s or 100 Mb/s operation, this
signal is always logic 0. There is no heartbeat function dur-
ing 10 Mb/s full duplex operation.
TRANSMIT CLOCK: 25 MHz Transmit clock outputs in
100BASE-TX mode or 2.5 MHz in 10BASE-T mode derived
from the 25 MHz reference clock.
TRANSMIT DATA: Transmit data MII input pins that accept
nibble data synchronous to the TX_CLK (2.5 MHz in
10BASE-T Mode or 25 MHz in 100BASE-TX mode).
TRANSMIT ENABLE: Active high input indicates the pres-
ence of valid nibble data on data inputs, TXD[3:0] for both
100 Mb/s or 10 Mb/s nibble mode.
TRANSMIT ERROR: In 100MB/s mode, when this signal is
high and the corresponding TX_EN is active the HALT sym-
bol is substituted for data.
In 10 Mb/s this input is ignored.
All DP83846A signal pins are I/O cells regardless of the
particular use. Below definitions define the functionality of
the I/O cells for each pin.
Type: I
Type: O
Type: I/O
Type OD
Type: PD,PU Internal Pulldown/Pullup
Type: S
Inputs
Outputs
Input/Output
Open Drain
Strapping Pin (All strap pins except PHY-
AD[0:4] have internal pull-ups or pull-
downs. If the default strap value is needed
to be changed then an external 5 k resistor
should be used. Please see Table 1.6 on
page 8 for details.)
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