dp83846a National Semiconductor Corporation, dp83846a Datasheet - Page 15

• Manufacturer Part Number: dp83846a
• Description: Dsphyter ? Single 10/100 Ethernet Transceiver
• Manufacturer: National Semiconductor Corporation

3.0 Functional Description
3.1 802.3u MII
The DP83846A incorporates the Media Independent Inter-
face (MII) as specified in Clause 22 of the IEEE 802.3u
standard. This interface may be used to connect PHY
devices to a MAC in 10/100 Mb/s systems. This section
describes both the serial MII management interface as well
as the nibble wide MII data interface.
The serial management interface of the MII allows for the
configuration and control of multiple PHY devices, gather-
ing of status, error information, and the determination of
the type and capabilities of the attached PHY(s).
The nibble wide MII data interface consists of a receive bus
and a transmit bus each with control signals to facilitate
data transfer between the PHY and the upper layer (MAC).
3.1.1 Serial Management Register Access
The serial management MII specification defines a set of
thirty-two 16-bit status and control registers that are acces-
sible through the management interface pins MDC and
MDIO. The DP83846A implements all the required MII reg-
isters as well as several optional registers. These registers
are fully described in Section 5. A description of the serial
management access protocol follows.
3.1.2 Serial Management Access Protocol
The serial control interface consists of two pins, Manage-
ment Data Clock (MDC) and Management Data Input/Out-
put (MDIO). MDC has a maximum clock rate of 25 MHz
and no minimum rate. The MDIO line is bi-directional and
For write transactions, the station management entity
writes data to the addressed DP83846A thus eliminating
the requirement for MDIO Turnaround. The Turnaround
time is filled by the management entity by inserting <10>.
Figure 4 shows the timing relationship for a typical MII reg-
ister write access.
Read Operation
Write Operation
MII Management
MDIO
MDIO
MDC
Serial Protocol
(STA)
(PHY)
Z
Idle
Z
0
Start
1 1
Opcode
(Read)
0 0
(PHYAD = 0Ch)
PHY Address
1 1 0 0 0 0 0 0 0
<idle><start><op code><device addr><reg addr><turnaround><data><idle>
<idle><01><10><AAAAA><RRRRR><Z0><xxxx xxxx xxxx xxxx><idle>
Figure 3. Typical MDC/MDIO Read Operation
<idle><01><01><AAAAA><RRRRR><10><xxxx xxxx xxxx xxxx><idle>
Table 4. Typical MDIO Frame Format
Register Address
(00h = BMCR)
Z
Z
Z
15
TA
0 0 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0
may be shared by up to 32 devices. The MDIO frame for-
mat is shown below in Table 4.
The MDIO pin requires a pull-up resistor (1.5 k ) which,
during IDLE and turnaround, will pull MDIO high. In order
to initialize the MDIO interface, the station management
entity sends a sequence of 32 contiguous logic ones on
MDIO to provide the DP83846A with a sequence that can
be used to establish synchronization. This preamble may
be generated either by driving MDIO high for 32 consecu-
tive MDC clock cycles, or by simply allowing the MDIO pull-
up resistor to pull the MDIO pin high during which time 32
MDC clock cycles are provided. In addition 32 MDC clock
cycles should be used to re-sync the device if an invalid
start, opcode, or turnaround bit is detected.
The DP83846A waits until it has received this preamble
sequence before responding to any other transaction.
Once the DP83846A serial management port has been ini-
tialized no further preamble sequencing is required until
after a power-on/reset, invalid Start, invalid Opcode, or
invalid turnaround bit has occurred.
The Start code is indicated by a <01> pattern. This assures
the MDIO line transitions from the default idle line state.
Turnaround is defined as an idle bit time inserted between
the Register Address field and the Data field. To avoid con-
tention during a read transaction, no device shall actively
drive the MDIO signal during the first bit of Turnaround. The
addressed DP83846A drives the MDIO with a zero for the
second bit of turnaround and follows this with the required
data. Figure 3 shows the timing relationship between MDC
and the MDIO as driven/received by the Station (STA) and
the DP83846A (PHY) for a typical register read access.
3.1.3 Serial Management Preamble Suppression
The DP83846A supports a Preamble Suppression mode
as indicated by a one in bit 6 of the Basic Mode Status
Register (BMSR, address 01h.) If the station management
entity (i.e. MAC or other management controller) deter-
mines that all PHYs in the system support Preamble Sup-
pression by returning a one in this bit, then the station
Register Data
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Z
Idle
Z