dp83840a National Semiconductor Corporation, dp83840a Datasheet - Page 65

• Manufacturer Part Number: dp83840a
• Description: 10/100 Mb/s Ethernet Physical Layer
• Manufacturer: National Semiconductor Corporation

Version A
6.0 Hardware User Information
7. Reduce the pull up/down resistance to 4.7k
the Phy Address stable at the latching time of 250ns. If the
capacitance at the node is large due to a particular
application, then the resistance will need to be lowered
even further.
Symptoms:
If the time constant at the Phy Address pins is in excess of
250ns then the proper hardware configurations values may
not be latched into the device after the software reset is
initiated.
Solution/Workaround:
Use 4.7k
PhyAddr pull up/down pins.
6.11 Receive Error Counter
Problem:
When receiving two back to back packets that have receive
errors (symbol errors), the DP83840A under certain
conditions records only the second symbol error (i.e. the
Receive Error Counter only gets incremented once for both
errors).
Description:
When a symbol error occurs at the very end of a packet, it
doesn't get reflected in the Receive Error Counter (Bits
15:0, Address 15h) until the next packet is in progress (an
internal synchronization issue between the receive clock
domain and the register clock domain). Normally, this isn't
a problem, the counter gets updated during the next
packet. The problem occurs when the packet with the “late”
symbol error backs up against another packet with a
symbol error. In that case, the counter only gets
incremented once for both errors.The end result is that the
counter misses a count.
Symptoms:
The Receive Error Counter, bits 15:0 in the Receive Error
Counter Register (15h), under certain conditions can
record a value in the register that is less than the true
receive error count.
Solution/Workaround:
There are no workarounds for this problem. This problem
will be fixed in future products.
6.12 Auto-Negotiation Test Compliancy
Problem:
During Auto-Negotiation conformance testing, by an
independent lab, four test conformance issues were
uncovered. We do not believe these four test
conformance issues will cause any system issues. The
four issues are:
1.) The part improperly enters the Acknowledge Detect
state upon receiving two groups of four inconsistent FLPs,
i.e.(the data in the FLPs alternate)
2.) The value of the nlp_test_min_timer is between 3.8ms
and 4.9ms, which is below the 5ms minimum requirement.
3.) The value of the data_detect_min_timer is valid except
when a pulse is received before the timer has expired.
4) The value of link_fail_inhibit_timer is 640ms, which is
below the 750ms minimum requirement.
resistors or resistors with lower values on all
(Continued)
to make
65
Description:
Described below are the four conformance tests that the
DP83840A failed. Currently IEEE does not have standard
tests to test for conformance. The tests performed by the
outside lab correspond to the four issues listed above.
Test 1: The DP83840A is sent two groups of four FLP
bursts
nlp_test_max_timer of 150ms. An example of the FLP
burst is shown below:
ABAB (Inter-group gap) ABAB
Where A represents a Link Code Word advertising a
technology such as 10 Mb/s half-duplex and B represents
a Link Code Word that is advertising a different technology
such as 100 Mb/s full-duplex.
When this ABAB (Inter-group gap) ABAB pattern is
received by the DP83840A, it will set the ACK bit.
Test 2: The DP83840A when sent four FLPs with a burst to
burst gap less than the 5ms speck. will set the ACK bit.
Test 3: The DP83840A when sent four FLPs with a
‘erroneous’ extra pulse after one of the clock pulses does
not ignore the extra pulse and as a result, the ACK bit is
not set.
Test 4: The DP83840A is sent a sequence of FLPs to
cause it to enter the FLP Link Good Check state. Upon
entering this state, the DP83840A should cease FLP
transmission and see all link_status indications as FAIL.
After
DP83840A
DP83840A failed the Link_fail_inhibit_timer test with a
value of 640ms which is below the 750ms limit.
Symptoms:
It is our opinion that the four issues found by the outside
lab will not affect system performance. Listed below are the
reasons we believe there will not be any system issues.
Issue 1: In a real network, the Auto-Negotiation protocol is
such that, once enabled, the FLP bursts should be sent
constantly, not in groups of 2, 4, 8, etc., with a number of
seconds in between FLP bursts (No inter-group gap). The
outside lab pointed out that the DP83840A implementation
works fine when the FLP bursts are constant, even if the
data within the bursts change.
Issue 2: The function of the NLP test timer is to ensure that
the FLP bursts are not spaced too close together and to
ensure that the data pulse to clock pulse timing is not too
long. The transmit specification for FLP burst spacing is
8ms min. Most, if not all applications center the FLP burst
spacing around 16ms. The data pulse to clock pulse timing
should be approximately 78 s maximum. As long as the
transmitter that is sending FLPs to the DP83840A is within
specifications, then having the NLP timer expire 1.2ms
early will not have any affect on Auto-Negotiation.
Issue 3: The extra ‘erroneous’ pulse is used to simulate
noise injected into the FLP stream which can potentially
corrupt the FLP burst. The Auto-Negotiation transmit
protocol requires the transmitter to send the same FLP
burst repeatedly (not just four times). Thus, if the
DP83840A receives an extra ‘erroneous’ pulse, then it will
take a few additional FLP bursts to set the ACK bit.
Issue 4: The link_fail_inhibit_timer is used to give the link a
chance to become good once a technology is selected.
The
DP83840A
link_timer
with
should
National Semiconductor
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