dp83840a National Semiconductor Corporation, dp83840a Datasheet - Page 13

• Manufacturer Part Number: dp83840a
• Description: 10/100 Mb/s Ethernet Physical Layer
• Manufacturer: National Semiconductor Corporation

Version A
2.0 Pin Description
2.8 PHY ADDRESS INTERFACE
The DP83840A PHYAD[4:0] inputs provide up to 32 unique PHY address options. An address selection of all zeros
(00000) will result in a PHY isolation condition. See the Isolate bit description in the BMCR, address 00h, Section 4.2
for further detail.
2.9 MISCELLANEOUS
PHYAD[0]
(LBEN)
PHYAD[1]
(ENCSEL)
PHYAD[2]
(CRS)
PHYAD[3]
(SPEED_100)
PHYAD[4]
(RX_ER)
RESET
LOWPWR
Signal Name
Signal Name
I = TTL/CMOS input
I/O, Z, J
I/O, Z, J
Type
I/O, J
I/O, J
I/O, J
Type
I, J
I, J
O = TTL/CMOS output
(Continued)
Pin #
Pin #
44
49
53
66
89
63
3
RESET: Active high input that initializes or reinitializes the DP83840A. See
section 3.10 for further detail.
LOW POWER MODE SELECT: Active high input that enables the low power
mode (100 Mb/s operation only). See section 3.13 for further detail.
PHY ADDRESS [0]: PHY address sensing pin (bit 0) for multiple PHY
applications. PHY address sensing is achieved by strapping a pull-up/pull-down
resistor (typically 4.7 k ) to this pin as required.
The pull-up/pull-down status of this pin is latched into the PHYAD address register
(address 19h) during power up/reset.
This pin is also the Loopback Enable output pin (LBEN) for the 100 Mb/s Serial
PMD Interface. See Section 2.2 for further detail.
PHY ADDRESS [1]: PHY address sensing pin (bit 1) for multiple PHY
applications. PHY address sensing is achieved by strapping a pull-up/pull-down
resistor (typically 4.7 k ) to this pin as required.
The pull-up/pull-down status of this pin is latched into the PHYAD address register
(address 19h) during power up/reset.
This pin is also the Encode Select output pin (ENCSEL) for the 100 Mb/s Serial
PMD Interface. See Section 2.2 for further detail.
PHY ADDRESS [2]: PHY address sensing pin (bit 2) for multiple PHY
applications. PHY address sensing is achieved by strapping a pull-up/pull-down
resistor (typically 4.7 k ) to this pin as required.
The pull-up/pull-down status of this pin is latched into the PHYAD address register
(address 19h) during power up/reset.
This pin is also the Carrier Sense output pin (CRS) for the MII Interface. See
Section 2.1 for further detail.
PHY ADDRESS [3]: PHY address sensing pin (bit 3) for multiple PHY
applications. PHY address sensing is achieved by strapping a pull-up/pull-down
resistor (typically 4.7 k ) to this pin as required.
The pull-up/pull-down status of this pin is latched into the PHYAD address register
(address 19h) during power up/reset.
This pin is also the Speed 100 Mb/s output pin (SPEED_100) for optional control
of peripheral circuitry. See Section 2.2 for further detail.
PHY ADDRESS [4]: PHY address sensing pin (bit 4) for multiple PHY
applications. PHY address sensing is achieved by strapping a pull-up/pull-down
resistor (typically 4.7 k ) to this pin as required.
The pull-up/pull-down status of this pin is latched into the PHYAD address register
(address 19h) during power up/reset.
This pin is also the Receive Error output pin (RX_ER) for the MII Interface. See
Section 2.1 for further detail.
Z = TRI-STATE output
13
J = IEEE 1149.1 pin
Description
Description
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