dp83840a National Semiconductor Corporation, dp83840a Datasheet - Page 46

• Manufacturer Part Number: dp83840a
• Description: 10/100 Mb/s Ethernet Physical Layer
• Manufacturer: National Semiconductor Corporation

Version A
4.0 Registers
4.3 BASIC MODE STATUS REGISTER (BMSR) (Continued)
4.4 PHY IDENTIFIER REGISTER #1 (PHYIDR1)
Address 02h
The PHY Identifier Registers #1 and #2 together form a unique identifier for the DP83840A. The Identifier consists of a
concatenation of the Organizationally Unique Identifier (OUI), the vendor's model number and the model revision
number. A PHY may return a value of zero in each of the 32 bits of the PHY Identifier if desired. The PHY Identifier is
intended to support network management.
National Semiconductor's IEEE assigned OUI is 080017h.
4.5 PHY IDENTIFIER REGISTER #2 (PHYIDR2)
Address 03h
Address 01h
15:10
15:0
9:4
3:0
Bit
Bit
Bit
0
Extended Capa-
VNDR_MDL
MDL_REV
OUI_MSB
Bit Name
Bit Name
Bit Name
OUI_LSB
bility
(Continued)
<01 0111>, RO/P OUI LEAST SIGNIFICANT BITS: Bits 19 to 24 of the OUI (080017h) are
<00 0000>, RO/P VENDOR MODEL NUMBER: Six bits of vendor model number mapped
0000 00>, RO/P
<00 1000 0000
<0001>, RO/P
1, RO/P
Default
Default
Default
EXTENDED CAPABILITY:
1 = Extended register capable
0 = Basic register capable only
OUI MOST SIGNIFICANT BITS: This register stores bits 3 to 18 of the
OUI (080017h) to bits 15 to 0 of this register respectively. The most
significant two bits of the OUI are ignored (the IEEE standard refers to
these as bits 1 and 2).
mapped to bits 15 to 10 of this register respectively.
to bits 9 to 4 (most significant bit to bit 9).
MODEL REVISION NUMBER: Four bits of vendor model revision
number mapped to bits 3 to 0 (most significant bit to bit 3). This field will
be incremented for all major DP83840A device changes.
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Description
Description
Description