dp83848qsqx/nopb National Semiconductor Corporation, dp83848qsqx/nopb Datasheet - Page 7

• Manufacturer Part Number: dp83848qsqx/nopb
• Description: Phyter Extended Temperature Single Port 10/100 Mb/s Ethernet Physical Layer Transceiver
• Manufacturer: National Semiconductor Corporation

MDC
MDIO
Signal Name
TX_CLK
TX_EN
TXD_0
TXD_1
TXD_2
TXD_3
RX_CLK
RX_DV
RX_ER
RXD_0
RXD_1
RXD_2
RXD_3
7.0 Pin Descriptions
The DP83848Q pins are classified into the following interface
categories (each interface is described in the sections that
follow):
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•
•
•
•
•
•
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Note: Strapping pin option. Please see Section
7.1 SERIAL MANAGEMENT INTERFACE
7.2 MAC DATA INTERFACE
Signal
Name
Serial Management Interface
MAC Data Interface
Clock Interface
LED Interface
Reset
Strap Options
10/100 Mb/s PMD Interface
Special Connect Pins
Power and Ground pins
TIONS
for strap definitions.
S, O, PD
S, O, PU
S, O, PD
Type
Type
I, PD
I, PD
I/O
O
O
I
I
Pin #
Pin #
25
24
31
32
34
36
37
38
39
2
3
4
5
6
7
MANAGEMENT DATA CLOCK: Synchronous clock to the MDIO management data input/
output serial interface which may be asynchronous to transmit and receive clocks. The
maximum clock rate is 25 MHz with no minimum clock rate.
MANAGEMENT DATA I/O: Bi-directional management instruction/data signal that may be
sourced by the station management entity or the PHY. This pin requires a 1.5 kΩ pullup resistor.
MII TRANSMIT CLOCK: 25 MHz Transmit clock output in 100 Mb/s mode or 2.5 MHz in 10
Mb/s mode derived from the 25 MHz reference clock.
Unused in RMII mode. The device uses the X1 reference clock input as the 50 MHz reference
for both transmit and receive.
MII TRANSMIT ENABLE: Active high input indicates the presence of valid data inputs on TXD
[3:0].
RMII TRANSMIT ENABLE: Active high input indicates the presence of valid data on TXD[1:0].
MII TRANSMIT DATA: Transmit data MII input pins, TXD[3:0], that accept data synchronous
to the TX_CLK (2.5 MHz in 10 Mb/s mode or 25 MHz in 100 Mb/s mode).
RMII TRANSMIT DATA: Transmit data RMII input pins, TXD[1:0], that accept data synchronous
to the 50 MHz reference clock.
MII RECEIVE CLOCK: Provides the 25 MHz recovered receive clocks for 100 Mb/s mode and
2.5 MHz for 10 Mb/s mode.
Unused in RMII mode. The device uses the X1 reference clock input as the 50 MHz reference
for both transmit and receive.
MII RECEIVE DATA VALID: Asserted high to indicate that valid data is present on the
corresponding RXD[3:0]. Mll mode by default with internal pulldown.
RMII Synchronous RECEIVE DATA VALID:This signal provide the RMII Receive Data Valid
indication independent of Carrier Sense.
MII RECEIVE ERROR: Asserted high synchronously to RX_CLK to indicate that an invalid
symbol has been detected within a received packet in 100 Mb/s mode.
RMII RECEIVE ERROR: Asserted high synchronously to X1 whenever an invalid symbol is
detected, and CRS_DV is asserted in 100 Mb/s mode.
This pin is not required to be used by a MAC in either MII or RMII mode, since the Phy is required
to corrupt data on a receive error.
MII RECEIVE DATA: Nibble wide receive data signals driven synchronously to the RX_CLK,
25 MHz for 100 Mb/s mode, 2.5 MHz for 10 Mb/s mode). RXD[3:0] signals contain valid data
when RX_DV is asserted.
RMII RECEIVE DATA: 2-bits receive data signals, RXD[1:0], driven synchronously to the X1
clock, 50 MHz.
Section 7.6 STRAP OP-
7
All DP83848Q signal pins are I/O cells regardless of the par-
ticular use. The definitions below define the functionality of
the I/O cells for each pin.
Type: I
Type: O
Type: I/O
Type OD
Type: PD,PU Internal Pulldown/Pullup
Type: S
Description
Description
Input
Output
Input/Output
Open Drain
Strapping Pin (All strap pins have weak
internal pull-ups or pull-downs. If the default
strap value is to be changed then an external
2.2 kΩ resistor should be used. Please see
Section
details.)
Section 7.6 STRAP OPTIONS
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