dp83848qsqx/nopb National Semiconductor Corporation, dp83848qsqx/nopb Datasheet - Page 68
dp83848qsqx/nopb
Manufacturer Part Number
dp83848qsqx/nopb
Description
Phyter Extended Temperature Single Port 10/100 Mb/s Ethernet Physical Layer Transceiver
Manufacturer
National Semiconductor Corporation
Datasheet
1.DP83848QSQXNOPB.pdf
(72 pages)
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T2.27.1
T2.27.2
T2.27.3
T2.27.4
T2.27.5
Parameter
15.2.27 RMII Receive Timing
Note: Per the RMII Specification, output delays assume a 25pF load.
Note: CRS_DV is asserted asynchronously in order to minimize latency of control signals through the Phy. CRS_DV may toggle synchronously at the end of the
Note: RX_DV is synchronous to X1. While not part of the RMII specification, this signal is provided to simplify recovery of receive data.
packet to indicate CRS deassertion.
X1 Clock Period
RXD[1:0], CRS_DV, RX_DV and
RX_ER output delay from X1 rising
CRS ON delay (100Mb)
CRS OFF delay (100Mb)
RXD[1:0] and RX_ER latency
(100Mb)
Description
50 MHz Reference Clock
From JK symbol on PMD
Receive Pair to initial assertion of
CRS_DV
From TR symbol on PMD
Receive Pair to initial deassertion
of CRS_DV
From symbol on Receive Pair.
Elasticity buffer set to default
value (01)
Notes
68
Min
2
18.5
Typ
20
27
38
Max
14
30152546
Units
bits
bits
bits
ns
ns
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