dp83848qsqx/nopb National Semiconductor Corporation, dp83848qsqx/nopb Datasheet - Page 13

• Manufacturer Part Number: dp83848qsqx/nopb
• Description: Phyter Extended Temperature Single Port 10/100 Mb/s Ethernet Physical Layer Transceiver
• Manufacturer: National Semiconductor Corporation

8.0 Configuration
This section includes information on the various configuration
options available with the DP83848Q. The configuration op-
tions described below include:
— Auto-Negotiation
— PHY Address and LED
— Half Duplex vs. Full Duplex
— Isolate mode
— Loopback mode
— BIST
8.1 AUTO-NEGOTIATION
The Auto-Negotiation function provides a mechanism for ex-
changing configuration information between two ends of a link
segment and automatically selecting the highest performance
mode of operation supported by both devices. Fast Link Pulse
(FLP) Bursts provide the signalling used to communicate Au-
to-Negotiation abilities between two devices at each end of a
link segment. For further detail regarding Auto-Negotiation,
refer to Clause 28 of the IEEE 802.3u specification. The
DP83848Q supports four different Ethernet protocols (10 Mb/
s Half Duplex, 10 Mb/s Full Duplex, 100 Mb/s Half Duplex,
and 100 Mb/s Full Duplex), so the inclusion of Auto-Negotia-
tion ensures that the highest performance protocol will be
selected based on the advertised ability of the Link Partner.
The Auto-Negotiation function within the DP83848Q can be
controlled either by internal register access or by the use of
the AN0 pin.
8.1.1 Auto-Negotiation Pin Control
The state of AN0 determines the specific mode advertised by
the DP83848Q as given in
ration options to be selected without requiring internal register
access.
The state of AN0 upon power-up/reset, determines the state
of bits [8:5] of the ANAR register.
The Auto-Negotiation function selected at power-up or reset
can be changed at any time by writing to the Basic Mode
Control Register (BMCR) at address 0x00h.
8.1.2 Auto-Negotiation Register Control
When Auto-Negotiation is enabled, the DP83848Q transmits
the abilities programmed into the Auto-Negotiation Advertise-
ment register (ANAR) at address 04h via FLP Bursts. Any
combination of 10 Mb/s, 100 Mb/s, Half-Duplex, and Full Du-
plex modes may be selected.
Auto-Negotiation Priority Resolution:
1.
2.
3.
4.
The Basic Mode Control Register (BMCR) at address 00h
provides control for enabling, disabling, and restarting the
Auto-Negotiation process. When Auto-Negotiation is dis-
abled, the Speed Selection bit in the BMCR controls switching
100BASE-TX Full Duplex (Highest Priority)
100BASE-TX Half Duplex
10BASE-T Full Duplex
10BASE-T Half Duplex (Lowest Priority)
AN0
TABLE 1. Auto-Negotiation Modes
0
1
10BASE-T Half-Duplex
100BASE-TX, Half-Duplex
10BASE-T, Half/Full-Duplex
100BASE-TX, Half/Full-Duplex
Advertised Mode
Table
1. This pin allows configu-
13
between 10 Mb/s or 100 Mb/s operation, and the Duplex
Mode bit controls switching between full duplex operation and
half duplex operation. The Speed Selection and Duplex Mode
bits have no effect on the mode of operation when the Auto-
Negotiation Enable bit is set.
The Link Speed can be examined through the PHY Status
Register (PHYSTS) at address 10h after a Link is achieved.
The Basic Mode Status Register (BMSR) indicates the set of
available abilities for technology types, Auto-Negotiation abil-
ity, and Extended Register Capability. These bits are perma-
nently set to indicate the full functionality of the DP83848Q
(only the 100BASE-T4 bit is not set since the DP83848Q does
not support that function).
The BMSR also provides status on:
•
•
•
•
The Auto-Negotiation Advertisement Register (ANAR) indi-
cates the Auto-Negotiation abilities to be advertised by the
DP83848Q. All available abilities are transmitted by default,
but any ability can be suppressed by writing to the ANAR.
Updating the ANAR to suppress an ability is one way for a
management agent to change (restrict) the technology that is
used.
The Auto-Negotiation Link Partner Ability Register (ANLPAR)
at address 0x05h is used to receive the base link code word
as well as all next page code words during the negotiation.
Furthermore, the ANLPAR will be updated to either 0081h or
0021h for parallel detection to either 100 Mb/s or 10 Mb/s re-
spectively.
The Auto-Negotiation Expansion Register (ANER) indicates
additional Auto-Negotiation status. The ANER provides sta-
tus on:
•
•
•
•
•
8.1.3 Auto-Negotiation Parallel Detection
The DP83848Q supports the Parallel Detection function as
defined in the IEEE 802.3u specification. Parallel Detection
requires both the 10 Mb/s and 100 Mb/s receivers to monitor
the receive signal and report link status to the Auto-Negotia-
tion function. Auto-Negotiation uses this information to con-
figure the correct technology in the event that the Link Partner
does not support Auto-Negotiation but is transmitting link sig-
nals that the 100BASE-TX or 10BASE-T PMAs recognize as
valid link signals.
If the DP83848Q completes Auto-Negotiation as a result of
Parallel Detection, bits 5 and 7 within the ANLPAR register
will be set to reflect the mode of operation present in the Link
Partner. Note that bits 4:0 of the ANLPAR will also be set to
00001 based on a successful parallel detection to indicate a
valid 802.3 selector field. Software may determine that nego-
tiation completed via Parallel Detection by reading a zero in
the Link Partner Auto-Negotiation Able bit once the Auto-Ne-
gotiation Complete bit is set. If configured for parallel detect
Whether or not Auto-Negotiation is complete
Whether or not the Link Partner is advertising that a
remote fault has occurred
Whether or not valid link has been established
Support for Management Frame Preamble suppression
Whether or not a Parallel Detect Fault has occurred
Whether or not the Link Partner supports the Next Page
function
Whether or not the DP83848Q supports the Next Page
function
Whether or not the current page being exchanged by Auto-
Negotiation has been received
Whether or not the Link Partner supports Auto-Negotiation
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