mpc5645s Freescale Semiconductor, Inc, mpc5645s Datasheet - Page 15

• Manufacturer Part Number: mpc5645s
• Description: Mpc5645s Microcontroller Data Sheet
• Manufacturer: Freescale Semiconductor, Inc

1.3.16
The RLE decoder is a crossbar slave sharing a slave port with the QuadSPI module. The platform eDMA is used to stream
compressed image data into and extract decompressed data out of the RLE Decoder.
1.3.17
The DRAM controller is a multi-port DRAM controller supporting LPDDR1, DDR-1, and DDR-2 memories. The DRAM
controller listens to the incoming requests to the seven buses in parallel and then sends commands to the DRAM from the
highest priority bus at the current time
The seven incoming 64-bit buses are:
The DRAM controller features the following:
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Programmable Timing Generation unit featuring 12 waveform generators allowing high degree of flexibility in panel
waveform generation
Reduced Swing Differential Signaling (RSDS) interface for RGB data and pixel clock
Conforms to “RSDS ‘Intra Panel’ Interface Specification” Rev. 1.0 (National Semiconductor)
Lossless decompression
Pixel formats supported: 8 bpp, 16 bpp, 24 bpp, and 32 bpp
AHB mapped read and write registers in RLE_DEC to achieve higher throughput
Programmable fill levels of read and write buffers for initiating burst transfers
Crop feature: Support for selectively reading out a part of decompressed image data taking complete compressed data
for the full image as input
DCU3
DCULite
e200z4d core — instruction bus
e200z4d core — data bus
VIU2
GFX2D
eDMA
Supports CAS latency of 2, 3, and 4 clock cycles
Master buses
— 7 incoming master buses
— Supports 16-byte and 32-byte bursts
— Supports byte enables
— Supports 4-bit priority signal for each bus
Write buffer contains five 32-byte entries
Supports 16-wide and 32-wide DDR1, DDR2, and LPDDR1 DRAM devices
Controller supports one chip select, 8-bank DRAM system
Supports dynamic on-die termination in the host device and in the DRAM
Supports memory sizes as small as 64 Mbit
RLE decoder
DRAM controller
MPC5645S Microcontroller Data Sheet, Rev. 6
Overview
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