mpc5645s Freescale Semiconductor, Inc, mpc5645s Datasheet - Page 119

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mpc5645s

Manufacturer Part Number
mpc5645s
Description
Mpc5645s Microcontroller Data Sheet
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1
2
3
4
5
6
7
8
Freescale Semiconductor
Num
10
DSPI timing specified at VDDE_x = 3.0 V to 3.6 V, T
Parameter values guaranteed by design.
The minimum SCK Cycle Time restricts the baud rate selection for given system clock rate.
The actual minimum SCK Cycle Time is limited by pad performance.
Maximum clock possible is System clock/2.
The maximum value is programmable in DSPI_CTARx[PSSCK] and DSPI_CTARx[CSSCK], program PSSCK=2 & CSSCK = 2
The maximum value is programmable in DSPI_CTARx[PASC] and DSPI_CTARx[ASC]
This delay value is corresponding to SMPL_PT=00b which is bit field 9 and 8 of DSPI_MCR register.
7
8
9
t
t
SUO
t
SUI
t
HO
HI
Symbol
CC
CC
CC
CC
2
2
2
2
C
D Data Setup Time for Inputs
D Data Hold Time for Inputs
D Data Valid (after SCK edge)
D Data Hold Time for Outputs
Master (MTFE = 0)
Slave
Master (MTFE = 1, CPHA = 0)
Master (MTFE = 1, CPHA = 1)
Master (MTFE = 0)
Slave
Master (MTFE = 1, CPHA = 0)
Master (MTFE = 1, CPHA = 1)
Master (MTFE = 0)
Slave
Master (MTFE = 1, CPHA=0)
Master (MTFE = 1, CPHA=1)
Master (MTFE = 0)
Slave
Master (MTFE = 1, CPHA = 0)
Master (MTFE = 1, CPHA = 1)
MPC5645S Microcontroller Data Sheet, Rev. 6
Table 67. DSPI Timing
Characteristic
A
= -40 to 105 °C, and CL = 50 pF with SRC = 0b10.
8
8
1
(continued)
Min
–15
–15
5.5
20
10
35
–4
10
26
–4
5
0
Max
15
20
30
15
Electrical characteristics
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SpecID
A11.10
A11.7
A11.8
A11.9
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