mpc5645s Freescale Semiconductor, Inc, mpc5645s Datasheet - Page 10

• Manufacturer Part Number: mpc5645s
• Description: Mpc5645s Microcontroller Data Sheet
• Manufacturer: Freescale Semiconductor, Inc

Overview
1.3.4
The eDMA module is a controller capable of performing complex data movements via 16 programmable channels, with
minimal intervention from the host processor. The hardware micro architecture includes a DMA engine which performs source
and destination address calculations, and the actual data movement operations, along with an SRAM-based memory containing
the transfer control descriptors (TCD) for the channels. This implementation is utilized to minimize the overall block size. The
eDMA module provides the following features:
1.3.5
The INTC (interrupt controller) provides priority-based preemptive scheduling of interrupt requests, suitable for statically
scheduled hard real-time systems.
For high priority interrupt requests, the time from the assertion of the interrupt request from the peripheral to when the processor
is executing the interrupt service routine (ISR) has been minimized. The INTC provides a unique vector for each interrupt
request source for quick determination of which ISR needs to be executed. It also provides an ample number of priorities so that
lower priority ISRs do not delay the execution of higher priority ISRs. To allow the appropriate priorities for each source of
interrupt request, the priority of each interrupt request is software configurable.
When multiple tasks share a resource, coherent accesses to that resource need to be supported. The INTC supports the priority
ceiling protocol for coherent accesses. By providing a modifiable priority mask, the priority can be raised temporarily so that
all tasks which share the resource can not preempt each other.
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— eDMA controller
— DCU
— DCULite
— VIU
— 2D Graphics Accelerator (GFX2D)
Seven slave ports:
— Platform Flash Controller (2 Ports)
— Platform SRAM Controller
— Graphics SRAM Controller (2 Ports)
— QuadSPI serial flash Controller and RLE Decoder
— Peripheral Bridge
32-bit internal address bus, 64-bit internal data bus
Programmable Arbitration Priority
— Requesting masters can be treated with equal priority and will be granted access to a slave port in round-robin
Temporary dynamic priority elevation of masters
16 channels support independent 8-, 16-, or 32-bit single value or block transfers
Supports variable sized queues and circular queues
Source and destination address registers are independently configured to post-increment or remain constant
Each transfer is initiated by a peripheral, CPU, periodic timer interrupt or eDMA channel request
Each DMA channel can optionally send an interrupt request to the CPU on completion of a single value or block
transfer
DMA transfers possible between system memories, QuadSPI, RLE Decoder, DSPIs, I
Purpose I/Os (GPIOs)
Programmable DMA Channel Mux allows assignment of any DMA source to any available DMA channel with up to
a total of 64 potential request sources
fashion, based upon the ID of the last master to be granted access, or a priority order can be assigned by software
at application run time
Enhanced Direct Memory Access (eDMA)
Interrupt Controller (INTC)
MPC5645S Microcontroller Data Sheet, Rev. 6
2
C, ADC, eMIOS, and General
Freescale Semiconductor