mpc8309 Freescale Semiconductor, Inc, mpc8309 Datasheet - Page 51

• Manufacturer Part Number: mpc8309
• Description: Powerquicc Ii Pro Integrated Communications Processor Family Hardware Specifications
• Manufacturer: Freescale Semiconductor, Inc

Figure 39
Figure 40
Figure 41
Freescale Semiconductor
At recommended operating conditions (see
Output hold times:
JTAG external clock to output high impedance:
Notes:
1. All outputs are measured from the midpoint voltage of the falling/rising edge of t
2. The symbols used for timing specifications follow the pattern of t
3. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.
4. Non-JTAG signal input timing with respect to t
5. Non-JTAG signal output timing with respect to t
6. Guaranteed by design and characterization.
The output timings are measured at the pins. All output timings assume a purely resistive 50-load (see
Time-of-flight delays must be added for trace lengths, vias, and connectors in the system.
inputs and t
timing (JT) with respect to the time data input signals (D) reaching the valid state (V) relative to the t
going to the high (H) state or setup time. Also, t
(D) went invalid (X) relative to the t
symbol representation is based on three letters representing the clock of a particular functional. For rise and fall times, the
latter convention is used with the appropriate letter: R (rise) or F (fall).
MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0
provides the AC test load for TDO and the boundary-scan outputs of the MPC8309.
provides the JTAG clock input timing diagram.
provides the TRST timing diagram.
Table 54. JTAG AC Timing Specifications (Independent of SYS_CLK_IN)
(first two letters of functional block)(reference)(state)(signal)(state)
External Clock
TRST
Parameter
JTAG
Output
Figure 39. AC Test Load for the JTAG Interface
JTG
Figure 40. JTAG Clock Input Timing Diagram
Boundary-scan data
Boundary-scan data
Table
VM
clock reference (K) going to the high (H) state. Note that, in general, the clock reference
t
JTKHKL
Figure 41. TRST Timing Diagram
2).
VM
VM = Midpoint Voltage (OV DD /2)
VM = Midpoint Voltage (OV DD /2)
JTDXKH
TCLK
Z
t
JTG
TCLK
0
TDO
TDO
= 50 
.
VM
.
symbolizes JTAG timing (JT) with respect to the time data input signals
t
TRST
Symbol
t
t
t
t
JTKLOX
JTKLDX
JTKLDZ
JTKLOZ
(first two letters of functional block)(signal)(state)(reference)(state)
VM
for outputs. For example, t
2
R
L
VM
= 50 
Min
TCLK
t
JTGR
2
2
2
2
to the midpoint of the signal in question.
OV
JTDVKH
DD
Max
t
JTGF
19
/2
—
—
9
1
(continued)
symbolizes JTAG device
JTG
clock reference (K)
Unit
Figure
ns
ns
39).
Notes
5, 6
5
6
for
JTAG
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