mpc8309 Freescale Semiconductor, Inc, mpc8309 Datasheet - Page 44

• Manufacturer Part Number: mpc8309
• Description: Powerquicc Ii Pro Integrated Communications Processor Family Hardware Specifications
• Manufacturer: Freescale Semiconductor, Inc

I
Figure 32
Figure 33
44
All values refer to V
2
Fall time of both SDA and SCL signals
Setup time for STOP condition
Bus free time between a STOP and START condition
Noise margin at the LOW level for each connected device (including
hysteresis)
Noise margin at the HIGH level for each connected device (including
hysteresis)
Notes:
1. The symbols used for timing specifications follow the pattern of t
2.
3. The maximum t
4. C
C
inputs and t
with respect to the time data input signals (D) reach the valid state (V) relative to the t
(H) state or setup time. Also, t
(S) went invalid (X) relative to the t
timing (I2) for the time that the data with respect to the stop condition (P) reaching the valid state (V) relative to the t
reference (K) going to the high (H) state or setup time. For rise and fall times, the latter convention is used with the appropriate
letter: R (rise) or F (fall).
MPC8309
the undefined region of the falling edge of SCL.
B
MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0
SDA
SCL
= capacitance of one bus line in pF.
provides the AC test load for the I
shows the AC timing diagram for the I
S
(first two letters of functional block)(reference)(state)(signal)(state)
provides a hold time of at least 300 ns for the SDA signal (referred to the V
IH
I2DVKL
(min) and V
t
I2CF
t
I2CL
t
I2SXKL
has only to be met if the device does not stretch the LOW period (t
Output
Parameter
IL
Table 44. I
(max) levels (see
I2SXKL
I2C
symbolizes I
clock reference (K) going to the low (L) state or hold time. Also, t
Figure 33. I
t
I2DXKL
2
C AC Electrical Specifications (continued)
Figure 32. I
Table
t
Z
I2DVKH
0
2
= 50 
t
43).
2
I2CH
C timing (I2) for the time that the data with respect to the start condition
2
C.
C Bus AC Timing Diagram
t
2
I2SXKL
2
C bus.
C AC Test Load
(first two letters of functional block)(signal)(state)(reference)(state)
for outputs. For example, t
Sr
Symbol
t
t
t
I2PVKH
I2SVKH
I2KHDX
t
V
V
I2CF
t
R
I2KHKL
NH
NL
L
= 50 
1
20 + 0.1 C
0.1  OV
0.2  OV
I2C
t
Min
clock reference (K) going to the high
0.6
1.3
I2PVKH
IH
OV
I2CL
(min) of the SCL signal) to bridge
I2DVKH
DD
DD
DD
t
I2CR
B
) of the SCL signal.
/2
4
symbolizes I
Freescale Semiconductor
I2PVKH
P
Max
300
—
—
—
—
t
I2CF
symbolizes I
2
C timing (I2)
S
I2C
Unit
s
s
ns
clock
V
V
for
2
C