mpc8309 Freescale Semiconductor, Inc, mpc8309 Datasheet - Page 30

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mpc8309

Manufacturer Part Number
mpc8309
Description
Powerquicc Ii Pro Integrated Communications Processor Family Hardware Specifications
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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Ethernet and MII Management
8.3.3
The IEEE 1588 DC timing specifications are given in
8.3.4
The IEEE 1588 AC timing specifications are given in
30
At recommended operating conditions with OV
QE_1588_CLK clock period
QE_1588_CLK duty cycle
QE_1588_CLK peak-to-peak jitter
Rise time QE_1588_CLK
(20%–80%)
Fall time QE_1588_CLK
(80%–20%)
QE_1588_CLK_OUT clock period
QE_1588_CLK_OUT duty cycle
QE_1588_PULSE_OUT
QE_1588_TRIG_IN pulse width
Notes:
1.T
2. It need to be at least two times of clock period of clock selected by TMR_CTRL[CKSEL]. See the MPC PowerQUICC II Pro
3. The maximum value of t
Output high voltage
Output low voltage
Output low voltage
Input high voltage
Input low voltage
Input current
PowerQUICC II Pro Integrated Processor Family Reference Manual, for a description of TMR_CTRL registers.
Integrated Processor Family Reference Manual, for a description of TMR_CTRL registers.
example, for 10/100 Mbps modes, the maximum value of t
RX_CLK
MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0
Parameter/Condition
is the max clock period of QUICC engine receiving clock selected by TMR_CTRL[CKSEL]. See the MPC
Characteristic
IEEE 1588
IEEE 1588 AC Specifications
T1588CLK
DC Specifications
Table 26. IEEE 1588 DC Electrical Characteristics
Table 27. IEEE 1588 AC Timing Specifications
is not only defined by the value of T
t
T1588CLKH
V
V
V
V
V
I
/t
IN
t
t
DD
t
t
t
T1588CLKOUT
T1588CLKOTH
OH
OL
OL
IH
IL
T1588CLKOUT
t
T1588CLKINR
T1588CLKINF
T1588CLKINJ
T1588TRIGH
t
t
Symbol
T1588CLK
of 3.3 V ± 300mV.
T1588OV
Symbol
/t
T1588CLK
0V ≤ V
2  t
I
T1588CLK
I
OH
I
OL
OL
Condition
2  t
= -8.0 mA
T1588CLK_MAX
Table
= 8.0 mA
Table
= 3.2mA
IN
T1588CLK
Min
2.5
1.0
1.0
0.5
40
30
≤ OV
is 3600 and 280ns, respectively.
RX_CLK
27.
27.
DD
, but also defined by the recovered clock. For
Typ
50
50
- 0.3
Min
2.4
2.0
T
RX_CLK
Max
250
2.0
2.0
3.0
60
70
OV
Freescale Semiconductor
DD
Max
 9
0.5
0.4
0.8
± 5
+ 0.3
Unit
ns
ps
ns
ns
ns
ns
ns
%
%
unit
μA
Notes
V
V
V
V
V
1, 3
2

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