mc68336 Freescale Semiconductor, Inc, mc68336 Datasheet - Page 42

• Manufacturer Part Number: mc68336
• Description: An Introduction To The Mc68331 And Mc68332
• Manufacturer: Freescale Semiconductor, Inc

4.5.2 GPT Initialization Example
The following example uses all five output compare channels. In this example, OC1 controls the OC1, OC2,
and OC3 pins. OC4 and OC5 operate independently. The period of OC1– OC3 is $200 TCNTs. The period
of OC4 is $400, and the period of OC5 is $800. The frequency of TCNT is the system clock divided by four.
Therefore, for a 16.778 MHz system clock, each TCNT tick is 238 ns long. Thus, the period of OC1– OC3
is approximately 122 s, and the periods of OC4 and OC5 are approximately 244 s and 488 s, respec-
tively.
This example is in the file “gpt_init.asm” in the archive “331_2ini.zip” on the Freeware Data System.
42
5. Set the interrupt enable bit for the channel in the timer interrupt mask register (TMSK1/2). This simply
To clear an interrupt, negate the appropriate interrupt status flag in the timer interrupt flag registers
(TFLG1/TFLG2). Read the flag in the asserted state and then write a zero to the bit. As long as the
interrupt status flag is set, the channel will continue to request interrupts.
involves writing the channel's bit number to a one.
#SIZING_ON
INITSYS:
INIT_GPT:
* TOC1 works differently than the other four OC channels because it can
* control all five OC channels. Here, it is configured to affect only the
* OC1 - OC3 channels. OC1 does not have the ability to toggle on a match.
* All of the OC channels are initialized with the same value so that
* the 5 square waves will be phase locked. Different offsets could be used
* for each channel. This would simply skew the square waves with respect
* to each other; they would still be frequency locked.
INIT_INTS:
WAI_FOR_INT:
* Each time that a match occurs between OC4 or OC5 and the Timer
* Counter (TCNT), the respective OC channel will toggle. If the software
* driver for the OC channel does not service an OC flag for some reason,
* a match will occur each 65,535 TCNT counts. OC1 is a special case. When
* it matches with TCNT, it will drive pins OC1-3 to the level written to
* the respective bits in the OC1D register.
* Following are the interrupt routines. In each one, a new future value
* is written into the appropriate TOC register.
OC5_INT:
INCLUDE
INCLUDE
INCLUDE
ORG
CLR.L
MOVEC
MOVE.B
CLR.B
MOVE.W
CLR.W
MOVE.W
MOVE.W
ADDI.W
MOVE.W
MOVE.W
MOVE.W
MOVE.W
MOVE.L
MOVE.L
MOVE.L
MOVE.W
MOVE.W
MOVE.W
ANDI.W
ORI.W
BRA
ADDI.W
'EQU331.ASM'
'INIT_RES.ASM'
'INIT_INT.ASM'
$400
Freescale Semiconductor, Inc.
D0
D0,VBR
#$7F,SYNCR
SYPCR
#$FF00,DDRGP
PACTL
#$3800,OC1M
TCNT,D0
#$200,D0
D0,TOC1
D0,TOC4
D0,TI4O5
#$5000,TCTL1
#OC1_INT,$210
#OC4_INT,$21C
#OC5_INT,$220
#$0085,GPTMCR
#$0680,ICR
#$C800,TMSK1
#$F0FF,SR
#$0500,SR
WAI_FOR_INT
#$400,TI4O5
For More Information On This Product,
Go to: www.freescale.com
;table of EQUates for common register addresses
;initialize reset vector
;initialize interrupt vectors
;begin program at $400, immediately after
;the exception table
;make sure that VBR is initialized to zero
;it is initialized to 0 out of reset
;set system clock to 16.78 MHz
;disable software watchdog
;make all GPT pins outputs, low at start
;set I4/O5 pins to output compare
;(this is the default value)
;set up value for OC1M/OC1D: OC1 controls
;OC1-3, data = 0 at match
;add offset to TCNT for delay before
;first compare
;store TCNT + Offset into TOC1
;store TCNT + Offset into TOC4
;store TCNT + Offset into TOC5
;OC 4 and 5 will toggle on compare
;Store interrupt routine addresses
;in the vector table (Note: this could
;be done in the file "init_int.asm".)
;set SUPV = 1, IARB = 5
;GPT priority = 6, base vector = $80
;TCNT is Sys Clk Div 4 (reset value)
;mask interrupts below level 6
;normally, this would go on to the next
;program task
;interrupt routine for OC5
;add #$400 to value in OC5 register
M68331/332TUT/D
MC68331/332