mc68336 Freescale Semiconductor, Inc, mc68336 Datasheet - Page 34

• Manufacturer Part Number: mc68336
• Description: An Introduction To The Mc68331 And Mc68332
• Manufacturer: Freescale Semiconductor, Inc

4.2.2 Clock Synthesizer Control Register (SYNCR)
SYNCR controls clock frequency, clock reference failure, clock signal usage during low-power stop, and fre-
quency of the 6800 bus clock output (ECLK). Configure SYNCR as follows.
4.2.3 System Protection Control Register (SYPCR)
SYPCR controls the software watchdog, which is enabled out of reset. This means that, unless the SWE bit
is cleared, a program must write the appropriate service sequence to the software service register (SWSR)
in a defined period or the MCU will reset each time the watchdog times out.
4.2.4 Periodic Interrupt Timer Register (PITR)
PITR and PICR control the periodic interrupt timer (PIT). The PIT begins to run when a timing modulus is
written to the PITM field in PITR. However, interrupt requests from the PIT are recognized only after an in-
terrupt priority level is written into the PIRQL field in the PICR. Clearing PITM stops the timer; clearing
PIRQL disables interrupts, but the timer continues to run. Because the CPU treats external interrupts as
SIM interrupt requests, PIT interrupts take precedence over external interrupts of the same priority. To use
the timer, proceed as follows.
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1. Set the state of the module mapping (MM) bit. Its reset state is a one, and can be written once. MM
2. If using the software watchdog, periodic interrupt timer, or the bus monitor, select action taken when
3. Select the interrupt arbitration level for the SIM with the interrupt arbitration (IARB) field. The default
1. Set frequency control bits (W,X,Y) to specify frequency. Ensure that the settings of these control bits
2. Select action to be taken during loss of crystal (RSTEN bit): activate a system reset or operate in limp
3. Select system clock during LPSTOP (STSIM and STEXT bits).
4. If using the ECLK, select the ECLK frequency (EDIV bit).
1. Disable the software watchdog, if desired, by clearing the SWE bit.
2. If the watchdog is enabled, perform the following actions.
3. Enable the double bus fault monitor, if desired (DATAFE bit or HME bit).
4. Enable the external bus monitor (BME bit) if desired.
5. Select the time-out period for bus monitor (BMT bits).
1. Make certain that there is a vector to the interrupt service routine in the exception vector table, and
2. Select whether or not to prescale the timer clock signal (PTP bit in PITR).
3. Select the timing modulus or interrupt rate (PITM field in PITR).
determines where the internal control registers are located in the system memory map. When MM =
0, register addresses range from $7FF000 to $7FFFFF; when MM =1, register addresses range from
$FFF000 to $FFFFFF.
FREEZE is asserted. The freeze software enable (FRZSW) bit determines whether the software
watchdog and periodic interrupt timer counters continue to run when FREEZE is asserted, and the
freeze bus monitor enable (FRZBM) bit determines whether the bus monitor continues to operate
when FREEZE is asserted.
state out of reset is $F, the highest precedence. To avoid spurious interrupts, each module request-
ing interrupts must have a unique, non-zero value in the IARB field. The CPU treats external interrupt
requests as SIM interrupts.
do not allow the VCO to exceed its maximum frequency of twice the maximum system clock frequen-
cy. The X bit determines whether the VCO runs at four times the system clock frequency (X = 1) or
twice the system clock frequency (X = 0). Thus, for system clock frequencies greater than 1/4 the
maximum VCO frequency, the X bit must be clear.
mode.
A. Choose whether to prescale the software watchdog clock (SWP bit).
B. Select the time-out period (SWT bits).
that there is a service routine at the address pointed to.
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M68331/332TUT/D
MC68331/332