mc68336 Freescale Semiconductor, Inc, mc68336 Datasheet - Page 33

• Manufacturer Part Number: mc68336
• Description: An Introduction To The Mc68331 And Mc68332
• Manufacturer: Freescale Semiconductor, Inc

the address is $0000. This example is in the file “init_int.asm” in the archive “331_2ini.zip” on the Freeware
Data System. This code can be assembled with the IASM32 assembler.
In the actual program code, the following routine must be included:
4.1.4 CPU Status Register
The CPU status register contains some very important information. The SR is discussed on page 2-3 of the
CPU32 Reference Manual (CPU32RM/AD). The fields are briefly described below:
4.2 Configuring the System Integration Module
Since the SIM determines important operating characteristics of the entire MCU, it should be the first module
after the CPU to be initialized. The following paragraphs discuss registersfor which correct initialization is
important.
4.2.1 System Integration Module Configuration Register (SIMCR)
The SIMCR controls module mapping for the MCU, internal use of the FREEZE signal, and the precedence
of simultaneous interrupt requests of the same priority. Configure the SIMCR as follows.
MC68331/332
M68331/332TUT/D
Trace Enable [15:14] — If enabled, these bits cause the CPU to generate a trace exception after each
instruction executes, allowing a debugging program to monitor the execution of a program under test.
Out of reset, tracing is disabled. See page 6-13 in the CPU32 Reference Manual (CPU32RM/AD) for
more details.
Supervisor/User State [13] — The MCU has two privilege levels: supervisor and user. Not all registers
and instructions are available at the user level. Most programs operate at the user level and then pass
control to a supervisor routine by causing an exception. Out of reset, the Supervisor/User State bit is
set, which means that the MCU is in supervisor mode. See pages 5-2 to 5-3 in the CPU32 Reference
Manual (CPU32RM/AD) for more details.
Interrupt Priority Level [10:8] — The interrupt priority level determines which interrupts are recognized
and which are masked. Level seven interrupts are always recognized. To allow other interrupts, this
field must contain a value that is lower than the interrupt priority level desired. For example, to allow
level 6 interrupts, the value must be %101 or less. Out of reset, the field has a value of %111, which
disables all interrupts except for level seven interrupts.
Condition Code Register [4:0] — The bits in the condition code register reflect the results of a previous
operation, and can be used for various condition tests, including conditional branches. There are ex-
tend, negative, zero, overflow, and carry bits.
INT
org
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
{code to handle}
{the exception}
{goes here}
RTE
$0008
$0000
INT
$0000
INT
$0000
INT
$0000
INT
$0000
INT
$0000
INT
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;put the following code in memory after the reset vector.
;The address of label INT is stored at location $0008,
;which is the bus error vector
;address error -- location $000C
;illegal instruction -- location $0010
;zero division -- location $0014
CHK, CHK2 Instructions -- location $0018
;Last User Defined Interrupt -- stored at location $03FC
;return to the code that was previously being executed
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