mc68hc908rf2 Freescale Semiconductor, Inc, mc68hc908rf2 Datasheet - Page 87

• Manufacturer Part Number: mc68hc908rf2
• Description: M68hc08 Microcontrollers Microcontroller / Transmitter
• Manufacturer: Freescale Semiconductor, Inc

MC68HC908RF2 — Rev. 4.0
MOTOROLA
Addr.
TRIM = written
$003A
$0038
$0039
Condition
ECGON = 0
ICGON = 0
ICGON = 1
N = written
CMON = 0
CMON = 1
ECGS = 0
us, uc, uw Register bit cannot be set, cleared, or written, respectively, in the given condition.
EOFF = 1
ICGS = 0
IOFF = 1
CMF = 1
CS = 0
CS = 1
(0), (1) Register bit must be clear or set, respectively, for the given condition to occur.
Reset
0*, 1* Register bit is temporarily forced clear or set, respectively, in the given condition.
ICG DCO Divider Control
ICG DCO Stage Register
Internal Clock Generator
0, 1 Register bit is forced clear or set, respectively, in the given condition.
Register Name
Trim Register (ICGTR)
— Register bit is unaffected by the given condition.
Register (ICGDVR)
CMIE CMF CMON CS ICGON ICGS ECGON ECGS N[6:0] TRIM[7:0] DDIV[3:0] DSTG[7:0]
(0)
(0)
—
—
—
—
—
us
us
—
—
0
0
0
0
See page 90.
See page 91.
See page 91.
(ICGDSR)
(1)
(0)
(0)
Table 6-5. ICG Module Register Bit Interaction Summary
—
—
—
—
—
—
1*
1*
0
0
0
0
Figure 6-10. ICG I/O Register Summary (Continued)
Reset:
Reset:
Reset:
Read:
Read:
Read:
Write:
Write:
Write:
(0)
(1)
(1)
(1)
(0)
(0)
—
—
—
us
us
0
1
0
0
Freescale Semiconductor, Inc.
For More Information On This Product,
(0)
(1)
uc
us
—
—
—
—
—
—
DSTG7
0
1
0
1
0
TRIM7
Bit 7
Internal Clock Generator Module (ICG)
R
1
0
Go to: www.freescale.com
(1)
(1)
(0)
(1)
—
—
—
—
—
—
1
1
1
1
1
Register Big Results for Given Condition
= Unimplemented
DSTG6
TRIM6
R
6
0
0
(0)
—
—
—
—
—
—
—
—
—
0*
0*
0
0
0
DSTG5
TRIM5
(0)
(1)
(1)
—
—
—
—
—
—
—
R
5
0
0
0
1
1
1
1
Unaffected by reset
DSTG4
TRIM4
(0)
—
—
—
—
—
—
—
—
—
—
—
0
0
0
R
R
4
0
0
$15
uw
uw
uw
uw
Internal Clock Generator Module (ICG)
—
—
—
—
—
—
—
—
—
—
= Reserved
DSTG3
TRIM3
DDIV3
U
3
0
$80
uw
uw
uw
uw
—
—
—
—
—
—
—
—
—
—
DSTG2
TRIM2
DDIV2
U
2
0
U = Unaffected
uw
uw
uw
uw
uw
uw
uw
—
—
—
—
—
—
—
—
DSTG1
TRIM1
DDIV1
U
1
0
I/O Registers
Data Sheet
DSTG0
TRIM0
DDIV0
uw
uw
uw
uw
uw
uw
uw
—
—
—
—
—
—
—
—
Bit 0
U
0
87