mc68hc908rf2 Freescale Semiconductor, Inc, mc68hc908rf2 Datasheet - Page 109

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mc68hc908rf2

Manufacturer Part Number
mc68hc908rf2
Description
M68hc08 Microcontrollers Microcontroller / Transmitter
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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9.2.2 Data Direction Register A
MC68HC908RF2 — Rev. 4.0
MOTOROLA
NOTE:
Data direction register A (DDRA) determines whether each port A pin is an input or
an output. Writing a 1 to a DDRA bit enables the output buffer for the corresponding
port A pin; a 0 disables the output buffer.
DDRA[7:0] — Data Direction Register A Bits
Avoid glitches on port A pins by writing to the port A data register before changing
data direction register A bits from 0 to 1.
Figure 9-4
When bit DDRAx is a 1, reading address $0000 reads the PTAx data latch. When
bit DDRAx is a 0, reading address $0000 reads the voltage level on the pin. The
data latch can always be written, regardless of the state of its data direction bit.
Table 9-1
Address:
These read/write bits control port A data direction. Reset clears DDRA[7:0],
configuring all port A pins as inputs.
Reset:
Read:
Write:
1 = Corresponding port A pin configured as output
0 = Corresponding port A pin configured as input
Freescale Semiconductor, Inc.
For More Information On This Product,
READ DDRA ($0004)
WRITE DDRA ($0004)
WRITE PTA ($0000)
READ PTA ($0000)
summarizes the operation of the port A pins.
shows the port A I/O logic.
DDRA7
$0004
Bit 7
0
Figure 9-3. Data Direction Register A (DDRA)
Go to: www.freescale.com
Input/Output (I/O) Ports
DDRA6
6
0
RESET
Figure 9-4. Port A I/O Circuit
DDRA5
5
0
DDRAx
DDRA4
PTAx
4
0
DDRA3
3
0
DDRA2
2
0
Input/Output (I/O) Ports
KBIE
DDRA1
1
0
X
PTAx
V
DD
Data Sheet
INTERNAL
PULLUP
DEVICE
DDRA0
Bit 0
Port A
0
109

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