mc68hc908rf2 Freescale Semiconductor, Inc, mc68hc908rf2 Datasheet - Page 83

• Manufacturer Part Number: mc68hc908rf2
• Description: M68hc08 Microcontrollers Microcontroller / Transmitter
• Manufacturer: Freescale Semiconductor, Inc

6.4.7 Improving Settling Time
MC68HC908RF2 — Rev. 4.0
MOTOROLA
The settling time of the internal clock generator can be vastly improved if an
external clock source can be used during the settling time. When the internal clock
generator is disabled (ICGON is low), the DDIV[3:0] and DSTG[7:0] bits can be
written. Then, when the internal clock generator is re-enabled, the clock period will
automatically start at the point written in the DDIV and DSTG bits.
Since a change in the DDIV and DSTG bits only cause a change in the clock period
relative to the starting point, the starting point must first be captured. The initial
clock period can be expressed as in the next example, where t
temperature, and voltage dependent constant and DDIV1 and DSTG1 are the
values of DDIV and DSTG when operating at t
Finding the new values for DDIV and DSTG is easy if the new clock period is a
binary multiple or fraction of the original. In this case, DSTG is unchanged and
DDIV2 is DDIV1 + log
If the new clock period is not a binary multiple or fraction of the original, both DSTG
and DDIV may need to change according to these equations:
If DSTG2 is greater than 255:
The software required to do this is relatively simple, since most of the math can be
done before coding because the initial and final clock periods are known. An
example of how to code this in assembly code is shown in
example is for illustrative purposes only and does not represent a valid syntax for
any particular assembler.
Freescale Semiconductor, Inc.
For More Information On This Product,
Internal Clock Generator Module (ICG)
DDIV2
Go to: www.freescale.com
2
(t
DSFACT
2
/t
DSTG2
DDIV2
=
DVFACT
1
t
1
).
DDIV2
=
t
X
=
=
=
⋅
+
2
DDIV1
DSFACT DSTG1
=
--------------------------------------------------- -
2
1
DDIV1
(
int
DDIV2 DDIV1
log
---------------------------
(
+
DSTG2
t
2
⋅
log
DVFACT
Internal Clock Generator Module (ICG)
1
DSTG1
(
⁄
⋅
.
–
t
t
2
2 ( )
1
⁄
)
t
1
)
=
DSTG2
-------------------- -
)
Figure
2
X
is a process,
6-9. This
Usage Notes
Data Sheet
83