cp3bt26y98nepx National Semiconductor Corporation, cp3bt26y98nepx Datasheet - Page 57
cp3bt26y98nepx
Manufacturer Part Number
cp3bt26y98nepx
Description
Reprogrammable Connectivity Processor With Bluetooth-r, Usb, And Can Interfaces
Manufacturer
National Semiconductor Corporation
Datasheet
1.CP3BT26Y98NEPX.pdf
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11.9.2
The PRSFC register is a byte-wide read/write register that
holds the 4-bit clock divisor used to generate the high-fre-
quency clock. In addition, the upper three bits are used to
control the operation of the PLL. The register is initialized to
4Fh at reset (except in PROG mode
FCDIV
MODE
Res
7
High Frequency Clock Prescaler Register
(PRSFC)
6
The Fast Clock Divisor specifies the divisor
used to obtain the high-frequency System
Clock from the PLL or Main Clock. The divisor
is (FCDIV + 1).
The PLL MODE field specifies the operation
mode of the on-chip PLL. After reset the
MODE bits are initialized to 100b, so the PLL
is configured to generate a 48-MHz clock.
This register must not be modified when the
System Clock is derived from the PLL Clock.
The System Clock must be derived from the
low-frequency oscillator clock while the
MODE field is modified.
MODE
MODE2:0
000
001
010
011
100
101
110
111
4
Reserved
Reserved
Reserved
36 MHz
48 MHz
60 MHz
Reserved
Reserved
(from 12 MHz
input clock)
Frequency
3
Output
.)
FCDIV
Reserved
Reserved
Reserved
3× Mode
4× Mode
5× Mode
Reserved
Reserved
Description
0
57
11.9.3
The PRSSC register is a byte-wide read/write register that
holds the clock divisor used to generate the Slow Clock from
the Main Clock. The register is initialized to B6h at reset.
SCDIV
11.9.4
The PRSAC register is a byte-wide read/write register that
holds the clock divisor values for prescalers used to gener-
ate the two auxiliary clocks from the Main Clock. The regis-
ter is initialized to FFh at reset.
ACDIV1
ACDIV2
7
7
Auxiliary Clock Prescaler Register (PRSAC)
Low Frequency Clock Prescaler Register
(PRSSC)
ACDIV2
The Slow Clock Divisor field specifies a divi-
sor to be used when generating the Slow
Clock from the Main Clock. The Main Clock is
divided by a value of (2 × (SCDIV + 1)) to ob-
tain the Slow Clock. At reset, the SCDIV reg-
ister is initialized to B6h, which generates a
Slow Clock rate of 32786.885 Hz. This is
about 0.5% faster than a Slow Clock generat-
ed from an external 32768 Hz crystal network.
The Auxiliary Clock Divisor 1 field specifies
the divisor to be used for generating Auxiliary
Clock 1 from the Main Clock. The Main Clock
is divided by a value of (ACDIV1 + 1).
The Auxiliary Clock Divisor 2 field specifies
the divisor to be used for generating Auxiliary
Clock 2 from the Main Clock. The Main Clock
is divided by a value of (ACDIV2 + 1).
4
SCDIV
3
ACDIV2
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