ml674000 Oki Semiconductor, ml674000 Datasheet - Page 17

• Manufacturer Part Number: ml674000
• Description: 32-bit Arm -based General Purpose Microcontroller
• Manufacturer: Oki Semiconductor

PWM
This MCU contains two PWM (Pulse Width Modulation) channels which can change duty cycle within a certain
fixed period. The PWM output resolution is 16 bits for each channel.
Serial Interface
This MCU contains two channels of serial interface.
(1) UART without FIFO: 1 channel
(2) UART with 16-byte FIFO: 1 channel
GPIO
This MCU contains two 16-bit parallel ports.
(1) Input or output can be selected for each bit.
(2) Interrupt can be used for all 16 bits of each channel, and both GPIO channels can be used as an interrupt
(3) Interrupt mask and interrupt mode (level) can be set for all bits.
(4) Configured as inputs immediately after reset.
AD Converter
This is a successive approximation type AD converter.
(1) 10 bits x 8 channels
(2) Sample and hold function
(3) Scan mode and select mode are supported
(4) Interrupt is generated after completion of conversion.
(5) Conversion time: 5 µs (min).
DMAC
This MCU contains a two channel direct memory access controller which transfers data between memory and
memory, between I/O and memory, and between I/O and I/O.
(1) Number of channels: 2 channels
(2) Channel priority level: Fixed mode
(3) Maximum number of transfers: 65,536 times (64K times)
(4) Data transfer size: Byte (8 bits), half-word (16 bits), word (32 bits)
(5) Bus request system:
(6) DMA transfer request: Software request: By setting the software transfer request bit within DMAC, the
(7) Interrupt request:
Oki Semiconductor
This serial interface is incorporated in µPLAT-7B.
This is ACE (Asynchronous Communication Element) equivalent in function to 16550A. It has 16-byte
FIFO in both sending and receiving.
input.
Channel priority level is always fixed (channel 0 > 1).
Round-robin
Priority level of the channel requested for transfer is kept lowest.
Cycle steal mode: Bus request signal is asserted for each DMA transfer cycle.
Burst mode:
External request: DMA transfer is started by external request allocated to each
Interrupt request is generated in CPU after the end of DMA transfers for the set
number of transfer cycles or after occurrence of error.
Interrupt request signal is output separately for each channel.
Interrupt request signal output can be masked for each channel.
are complete.
CPU starts DMA transfer.
channel.
Bus request signal is asserted until all transfers of transfer cycles
ML674000
15/22