ml674000 Oki Semiconductor, ml674000 Datasheet - Page 14

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ml674000

Manufacturer Part Number
ml674000
Description
32-bit Arm -based General Purpose Microcontroller
Manufacturer
Oki Semiconductor
Datasheet

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Oki Semiconductor
Pin Name
DMA control signals
DREQ0
DREQCLR0
TCOUT0
DREQ1
DREQCLR1
TCOUT1
Serial IO Interface
STXD
SRXD
UART
SIN
SOUT
CTS
DSR
DCD
DTR
RTS
RI
I/O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
Ch 0 DMA request signal, used when DMA controller configured for DREQ
type
Ch 0 DREQ signal clear request. The DMA device responds to this output
by negating DREQ.
Indicates to Ch 0 DMA device that last transfer has started
Ch 1 DMA request signal, used when DMA controller configured for DREQ
type
Ch 1 DREQ signal clear request. The DMA device responds to this output
by negating DREQ.
Indicates to Ch 1 DMA device that last transfer has started
SIO transmit signal
SIO receive signal
Serial data input
Serial data output
Clear To Send.
Indicates that modem or data set is ready to transfer data.
Bit 4 in modem status register reflects this input.
Data Set Ready.
Indicates that modem or data set is ready to establish a communications
link with UART.
Bit 5 in modem status register reflects this input.
Data Carrier Detect.
Indicates that modem or data set has detected data carrier signal.
Bit 7 in modem status register reflects this input.
Data Terminal Ready.
Indicates that UART is ready to establish a communications link with
modem or data set.
Bit 0 in modem control register controls this output.
Request To Send.
Indicates that UART is ready to transfer data to modem or data set.
Bit 1 in modem control register controls this output.
Ring Indicator.
Indicates that modem or data set has received telephone ring indicator.
Bit 6 in modem status register reflects this input.
Description
Secondary
Secondary
Secondary
Secondary
Secondary
Secondary
Secondary
Secondary
Secondary
Secondary
Secondary
Secondary
Secondary
Secondary
Secondary
Secondary
Secondary
Primary/
ML674000
Negative
Negative
Negative
Negative
Negative
Negative
Positive
Positive
Positive
Positive
Positive
Positive
Positive
Positive
Positive
Positive
Logic
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