cy8c20111 Cypress Semiconductor Corporation., cy8c20111 Datasheet - Page 19

• Manufacturer Part Number: cy8c20111
• Manufacturer: Cypress Semiconductor Corporation.

7.22 I2C_ADDR_DM
I2C_ADDR_DM: 7Ch
This register sets the drive mode of I
value written to register 7Ch is applied only after locking register 79h again.
7.23 CS_READ_BUTTON
I2C_ADDR_DM : 81h
The scan result of a CapSense input (raw count, difference count, and baseline) can be read only for one input at a time using 82h-87h
registers. This register is used to select a CapSense input to read the raw count, difference count, and baseline. Only the pins defined
as CapSense inputs in register 07h can be used with this register. Trying to select other pins not defined as CapSense does not have
any change.
Document Number: 001-53516 Rev. **
Bit
7
6:0
Bit
7
1:0
Access: FD
Access: FD
Access: FD
1 Button
Bit Name
1 Button
Bit Name
2 Button
Bit Name
Device I
Button Select Register
2
C Address and I
Name
Name
I2CIP_EN
I2CIP_EN
I2C_ADDR [6:0]
RD_EN
CSBN [1:0]
RD_EN
RD_EN
RW: 0
RW: 0
RW: 0
7
7
7
2
C Pin Drive Mode Register
6
6
6
2
C pins and I
2
5
5
5
PRELIMINARY
C slave address. To write to this register, register 79h must first be unlocked. The
This bit is used to set the I
0
1
Used to set the device I
This bit enables the CapSense raw data reading.
0
1
These bits decide which CapSense button scan result are read. When writing to this
register, the bitmask must contain only one bit set to ’1’, otherwise the data is
discarded.
Description
Description
01
10
CSBN [1:0]
4
4
4
Disable CapSense scan result reading
Enable CapSense scan result reading
Internal pull up enabled
Internal pull up disabled
I2C_ADDR[6:0]
RW: 00
3
3
3
1
2
2
CapSense Button No
C address.
2
C pins drive mode.
2
2
2
CY8C20111, CY8C20121
1
1
1
CSBN[1:0]
RW: 00
CSBN[0]
RW: 0
0
0
0
Page 19 of 34
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