cy8c20111 Cypress Semiconductor Corporation., cy8c20111 Datasheet - Page 12

• Manufacturer Part Number: cy8c20111
• Manufacturer: Cypress Semiconductor Corporation.

7.5 OP_SEL_x
This register is used to enable logic operation on GP outputs. OP_SEL_0 should be configured to get the logic operation output on
DIG0 output and OP_SEL_1 for DIG1 output. Write to these registers during the disable state of respective DIG output pins does not
have any effect.
The input to the logic operation can be selected in LOGIC_OPRX registers. The selected inputs can be ORed or ANDed. The output
of logic operation can also be inverted.
7.6 LOGICAL_OPR_INPUTx
LOGICAL_OPR_INPUT0: 1Eh
LOGICAL_OPR_INPUT0
LOGICAL_OPR_INPUT1
These registers are used to give the input to logic operation block. The inputs can be only CapSense input status.
Document Number: 001-53516 Rev. **
OP_SEL_0: 1Ch
Bit
7
1
0
Bit
1:0
Access: FD
Access: FD
Access: FD
Access: FD
1/2Button
Bit Name
1 Button
Bit Name
2 Button
Bit Name
2 Button
Bit Name
Selects Input for Logic Operation
Logic Operation Selection Registers
Op_En
InvOp
Operator
Name
CSL [1:0]
Name
Op_En
RW: 0
7
7
7
7
OP_SEL_1: 21h (Not available for 1 Button)
LOGICAL_OPR_INPUT1: 23h (Not available for 1 button)
6
6
6
6
5
5
5
5
PRELIMINARY
This bit enables or disables logic operation.
0
1
This bit enables or disables logic operation output inversion.
0
1
This bit selects which operator should be used to compute logic operation.
0
1
Description
These bits selects the input for logic operation block.
Description
4
4
4
4
Disable logic operation
Enable logic operation
Logic operation output not inverted
Logic operation output inverted
Logic operator OR is used on inputs
Logic operator AND is used on inputs
3
3
3
3
2
2
2
2
CY8C20111, CY8C20121
RW: 0
InvOp
1
1
1
1
CSL [1:0]
CSL [1:0]
RW:01
RW:02
Operator
CSL[0]
RW:01
RW: 0
0
0
0
0
Page 12 of 34
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