cy8c20436an-24lqxit Cypress Semiconductor Corporation., cy8c20436an-24lqxit Datasheet - Page 16

• Manufacturer Part Number: cy8c20436an-24lqxit
• Description: Capsense Applications
• Manufacturer: Cypress Semiconductor Corporation.

48-Pin QFN OCD
The 48-pin QFN part is for the CY8C20066A On-Chip Debug (OCD) PSoC device. Note that this part is only used for in-circuit
debugging.
Table 10. Pin Definitions - CY8C20066A PSoC Device
1. This part is available in limited quantities for In-Circuit Debugging during prototype development. It is not available in production volumes.
2. The center pad (CP) on the QFN package must be connected to ground (V
3. On Power Up , the SDA(P1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. The SCL(P1[1])line drives
4. Alternate SPI clock.
Document Number: 001-54459 Rev. *D
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LEGEND A = Analog, I = Input, O = Output, NC = No Connection H = 5 mA High Output Drive, R = Regulated Output.
must be electrically floated and not connected to any other signal.
resistive low for 512 sleep clock cycles and both the pins transition to High impedance state . On reset, after XRES de- asserts, the SDA and the SCL lines drive
resistive low for 8 sleep clock cycles and transition to high impedance state. In both cases, a pull up resistance on these lines combines with the pull down resistance
(5.6K ohm) and form a potential divider. Hence, during power up or reset event, P1[1] and P1[0] may disturb the I2C bus. Use alternate pins if you encounter issues.
IOHR
IOHR
IOHR
IOHR
IOHR
IOHR
IOHR
IOHR
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Power
Power
Input
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
OCDOE
P2[7]
P2[5]
P2[3]
P2[1]
P4[3]
P4[1]
P3[7]
P3[5]
P3[3]
P3[1]
P1[7]
P1[5]
CCLK
HCLK
P1[3]
P1[1]
V
D+
D-
V
P1[0]
P1[2]
P1[4]
P1[6]
XRES
P3[0]
P3[2]
P3[4]
P3[6]
P4[0]
P4[2]
P2[0]
P2[2]
P2[4]
P2[6]
SS
DD
Crystal output (XOut)
Crystal input (XIn)
OCD high speed clock output
Ground connection
USB D+
USB D-
Supply voltage
(EXTCLK)
Active high external reset with
internal pull down
OCD mode direction pin
I
I
OCD CPU clock output
SPI CLK.
ISSP CLK
ISSP DATA
Optional external clock input
2
2
C SCL, SPI SS
C SDA, SPI MISO
[3],
[3]
I
, I
2
C SCL, SPI MOSI
2
C SDA, SPI CLK
[1, 2]
[4]
SS
) for best mechanical, thermal, and electrical performance. If not connected to ground, it
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CP
AI, I2 C SCL, SPI SS, P1[7]
IOH
IOH
IOH
IOH
IOH
IOH
IOH
IOH
Power
Power
Power
AI, XOut, P2[5]
AI, XIn , P2[3]
Figure 11. CY8C20066A PSoC Device
I
I
I
I
I
I
I
I
AI , P2[1]
AI , P4[3]
AI , P4[1]
AI , P3[7]
AI , P3[5]
AI , P3[3]
AI , P3[1]
A
I
OCDO
, P2[7]
P0[0]
P0[2]
P0[4]
P0[6]
V
OCDO
OCDE
P0[7]
P0[5]
P0[3]
V
P0[1]
V
E
DD
SS
SS
CY8C20X36A/46A/66A/96A
1
2
3
4
5
6
7
8
9
10
11
12
Supply voltage
OCD even data I/O
OCD odd data output
Integrating input
Ground connection
Center pad must be connected to ground
( Top View )
QFN
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[+] Feedback
P2[6] , AI
P2[4] , AI
P2[2] , AI
P2[0] , AI
P4[2] , AI
P4[0] , AI
P3[6] , AI
P3[4] , AI
P3[2] , AI
P3[0] , AI
P1[6] , AI
XRES