cy8c20436an-24lqxit Cypress Semiconductor Corporation., cy8c20436an-24lqxit Datasheet - Page 10

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cy8c20436an-24lqxit

Manufacturer Part Number
cy8c20436an-24lqxit
Description
Capsense Applications
Manufacturer
Cypress Semiconductor Corporation.
Datasheet
30-Ball Part Pinout
Table 4. CY8C20766A, CY8C20746A 30-Ball Part Pinout (WLCSP)
1. On power up , the SDA(P1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. The SCL(P1[1])line drives
2. Alternate SPI clock.
Document Number: 001-54459 Rev. *D
Pin No.
A1
A2
A3
A4
A5
B1
B2
B3
B4
B5
C1
C2
C3
C4
C5
D1
D2
D3
D4
D5
E1
E2
E3
E4
E5
F1
F2
F3
F4
F5
resistive low for 512 sleep clock cycles and both the pins transition to high impedance state. On reset, after XRES de-asserts, the SDA and the SCL lines drive
resistive low for 8 sleep clock cycles and transition to high impedance state. Hence, during power up or reset event, P1[1] and P1[0] may disturb the I2C bus. Use
alternate pins if you encounter issues.
Digital
IOHR
IOHR
IOHR
IOHR
IOHR
IOHR
IOHR
IOHR
IOH
IOH
IOH
IOH
IOH
IOH
IOH
IOH
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Power
Power
Type
Input
Analog
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Name
XRES
P0[2]
P0[6]
P0[1]
P2[7]
P2[6]
P0[0]
P0[4]
P0[3]
P2[5]
P2[2]
P2[4]
P0[7]
P0[5]
P2[3]
P2[0]
P3[0]
P3[1]
P3[3]
P2[1]
P1[6]
P1[4]
P1[7]
P1[5]
P1[2]
P1[0]
P1[1]
P1[3]
V
V
DD
SS
Supply voltage
Integrating Input
Integrating Input
Crystal Output (Xout)
Crystal Input (Xin)
Active high external reset with
internal pull down
Optional external clock input
(EXT CLK)
I
I
ISSP DATA
CLK
Supply ground
ISSP CLK
MOSI
SPI CLK
2
2
C SCL, SPI SS
C SDA, SPI MISO
[2]
Description
[1]
[1]
, I
, I
2
C SCL, SPI
2
C SDA, SPI
Figure 5. CY8C20766A 30-Ball WLCSP
CY8C20X36A/46A/66A/96A
A
B
C
D
E
F
5
1
Bottom View
4
Top View
2
3
3
2
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A
B
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