xc2v1000-4fg256c Xilinx Corp., xc2v1000-4fg256c Datasheet - Page 81
xc2v1000-4fg256c
Manufacturer Part Number
xc2v1000-4fg256c
Description
Virtex-ii Platform Fpgas
Manufacturer
Xilinx Corp.
Datasheet
1.XC2V1000-4FG256C.pdf
(318 pages)
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Virtex-II Pin-to-Pin Input Parameter Guidelines
All devices are 100% functionally tested. Listed below are representative values for typical pin locations and normal clock
loading. Values are expressed in nanoseconds unless otherwise noted.
Global Clock Setup and Hold for LVTTL Standard, With DCM
Table 36: Global Clock Setup and Hold for LVTTL Standard, With DCM
DS031-3 (v3.5) November 5, 2007
Product Specification
Notes:
1. IFF = Input Flip-Flop or Latch
2. Setup time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is measured
Input Setup and Hold Time Relative
to Global Clock Input Signal for
LVTTL Standard.
For data input with different
standards, adjust the setup time
delay by the values shown in
Input Switching Characteristics
Standard Adjustments, page
No Delay
Global Clock and IFF with DCM
relative to the Global Clock input signal with the slowest route and heaviest load.
Description
R
11.
IOB
T
PSDCM
Symbol
/T
PHDCM
www.xilinx.com
Virtex-II Platform FPGAs: DC and Switching Characteristics
XC2V1000
XC2V1500
XC2V2000
XC2V3000
XC2V4000
XC2V6000
XC2V8000
XC2V250
XC2V500
XC2V40
XC2V80
Device
1.60/–0.90
1.60/–0.90
1.60/–0.90
1.60/–0.90
1.60/–0.90
1.60/–0.90
1.70/–0.90
1.70/–0.90
1.70/–0.90
1.70/–0.90
-6
Speed Grade
1.60/–0.90
1.60/–0.90
1.60/–0.90
1.60/–0.90
1.60/–0.90
1.60/–0.90
1.70/–0.90
1.70/–0.90
1.70/–0.90
1.70/–0.90
1.70/–0.90
-5
1.84/–0.76
1.84/–0.76
1.84/–0.76
1.84/–0.76
1.84/–0.76
1.84/–0.76
1.96/–0.76
1.96/–0.76
1.96/–0.76
1.96/–0.76
1.96/–0.76
-4
Module 3 of 4
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
33
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