xc2v1000-4fg256c Xilinx Corp., xc2v1000-4fg256c Datasheet - Page 10

• Manufacturer Part Number: xc2v1000-4fg256c
• Description: Virtex-ii Platform Fpgas
• Manufacturer: Xilinx Corp.

Table 2: Supported Differential Signal I/O Standards
Table 3: Supported DCI I/O Standards
DS031-2 (v3.5) November 5, 2007
Product Specification
Notes:
1.
Notes:
1. LVDCI_XX and LVDCI_DV2_XX are LVCMOS controlled
2. These are SSTL compatible.
3.
4.
LVPECL_33
LDT_25
LVDS_33
LVDS_25
LVDSEXT_33
LVDSEXT_25
BLVDS_25
ULVDS_25
LVDCI_33
LVDCI_DV2_33
LVDCI_25
LVDCI_DV2_25
LVDCI_18
LVDCI_DV2_18
LVDCI_15
LVDCI_DV2_15
GTL_DCI
GTLP_DCI
HSTL_I_DCI
HSTL_II_DCI
HSTL_III_DCI
HSTL_IV_DCI
HSTL_I_DCI_18
HSTL_II_DCI_18
HSTL_III_DCI_18
HSTL_IV_DCI_18
SSTL18_I_DCI
SSTL18_II_DCI
SSTL2_I_DCI
SSTL2_II_DCI
SSTL3_I_DCI
SSTL3_II_DCI
LVDS_25_DCI
LVDSEXT_25_DCI
I/O Standard
N/R = no requirement.
impedance buffers, matching the reference resistors or half of
the reference resistors.
SSTL18_I is not a JEDEC-supported standard.
N/R = no requirement.
Standard
I/O
(1)
(1)
(1)
(1)
R
(2)
(2)
(2)
(2)
(3)
(1)
(1)
(1)
(1)
Output
Output
V
V
CCO
3.3
2.5
3.3
2.5
3.3
2.5
2.5
2.5
CCO
3.3
3.3
2.5
2.5
1.8
1.8
1.5
1.5
1.2
1.5
1.5
1.5
1.5
1.5
1.8
1.8
1.8
1.8
1.8
1.8
2.5
2.5
3.3
3.3
2.5
2.5
Input
V
N/R
Input
V
N/R
N/R
N/R
N/R
N/R
N/R
N/R
3.3
3.3
2.5
2.5
1.8
1.8
1.5
1.5
1.2
1.5
1.5
1.5
1.5
1.5
1.8
1.8
1.8
1.8
1.8
1.8
2.5
2.5
3.3
3.3
2.5
2.5
CCO
CCO
(1)
Input
Input
N/R
V
V
0.75
0.75
1.25
1.25
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
1.0
0.9
0.9
1.1
0.9
0.8
0.9
0.9
1.1
0.9
1.5
1.5
REF
REF
(4)
Termination
0.490 - 1.220
0.500 - 0.700
0.250 - 0.400
0.250 - 0.400
0.440 - 0.820
0.440 - 0.820
0.250 - 0.450
0.500 - 0.700
Output
Series
Series
Series
Series
Series
Series
Series
Series
Single
Single
Single
Single
Single
Single
Type
V
Split
Split
Split
Split
Split
Split
Split
Split
Split
Split
Split
Split
OD
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Logic Resources
IOB blocks include six storage elements, as shown in
Figure
Each storage element can be configured either as an
edge-triggered D-type flip-flop or as a level-sensitive latch.
On the input, output, and 3-state path, one or two DDR reg-
isters can be used.
Double data rate is directly accomplished by the two regis-
ters on each path, clocked by the rising edges (or falling
edges) from two different clock nets. The two clock signals
are generated by the DCM and must be 180 degrees out of
phase, as shown in
and 3-state data signals, each being alternately clocked out.
Virtex-II Platform FPGAs: Functional Description
2.
OCK2
OCK2
OCK1
OCK1
Reg
Reg
Reg
Reg
Figure 2: Virtex-II IOB Block
DDR mux
DDR mux
3-State
Output
Figure
3. There are two input, output,
IOB
ICK1
ICK2
Reg
Reg
Input
PAD
DS031_29_100900
Module 2 of 4
2