ep2sgx60e Altera Corporation, ep2sgx60e Datasheet - Page 42

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ep2sgx60e

Manufacturer Part Number
ep2sgx60e
Description
4. Serial Configuration Devices Epcs1, Epcs4, Epcs16, Epcs64, And Epcs128 Data Sheet
Manufacturer
Altera Corporation
Datasheet

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Pin Information
4–42
Configuration Handbook, Volume 2
DATA
ASDI
nCS
Table 4–31. Serial Configuration Device Pin Description (Part 1 of 2)
Name
Pin
Pin Number
2
5
1
Package
in 8-Pin
SOIC
Pin Number
8
15
7
in 16-Pin
Package
SOIC
Figure 4–21. Altera Serial Configuration Device 16-Pin SOIC Package Pin-Out
Diagram
Note to
(1)
These pins can be left floating or connected to V
convenient on the board.
Pin Type
Output
Input
Input
Figure
4–21:
The
configuration device to the FPGA during read/configuration
operation. During a read/configuration operations, the serial
configuration device is enabled by pulling
signal transitions on the falling edge of
The AS data input signal is used to transfer data serially into the
serial configuration device. It receives the data that should be
programmed into the serial configuration device. Data is latched
on the rising edge of
The active low chip select input signal toggles at the beginning
and end of a valid instruction. When this signal is high, the
device is deselected and the
signal is low, it enables the device and puts the device in an
active mode. After power up, the serial configuration device
requires a falling edge on the
operation.
DATA
DATA
N.C.
N.C.
N.C.
N.C.
V
V
nCS
CC
CC
output signal transfers data serially out of the serial
or EPCS128
EPCS64,
2
3
4
5
6
7
8
EPCS16,
1
(1)
(1)
(1)
(1)
DCLK
14
13
12
11
10
9
16
15
Description
(1)
(1)
(1)
(1)
.
DATA
nCS
CC
DCLK
ASDI
N.C.
N.C.
N.C.
N.C.
GND
V
CC
or GND, whichever is more
signal before beginning any
pin is tri-stated. When this
DCLK
nCS
Altera Corporation
.
low. The
May 2008
DATA

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