ep2c35 Altera Corporation, ep2c35 Datasheet - Page 63

• Manufacturer Part Number: ep2c35
• Description: Cyclone Ii Device Family Data Sheet
• Manufacturer: Altera Corporation

Altera Corporation
February 2007
Slew Rate Control
Slew rate control is performed by using programmable output drive
strength.
Bus Hold
Each Cyclone II device user I/O pin provides an optional bus-hold
feature. The bus-hold circuitry can hold the signal on an I/O pin at its
last-driven state. Since the bus-hold feature holds the last-driven state of
the pin until the next input signal is present, an external pull-up or
pull-down resistor is not necessary to hold a signal level when the bus is
tri-stated.
The bus-hold circuitry also pulls undriven pins away from the input
threshold voltage where noise can cause unintended high-frequency
switching. You can select this feature individually for each I/O pin. The
bus-hold output drives no higher than V
signals.
1
The bus-hold circuitry is only active after configuration. When going into
user mode, the bus-hold circuit captures the value on the pin present at
the end of configuration.
The bus-hold circuitry uses a resistor with a nominal resistance (R
approximately 7 kΩ to pull the signal level to the last-driven state. Refer
to the DC Characteristics & Timing Specifications chapter in Volume 1 of the
Cyclone II Device Handbook for the specific sustaining current for each
V
used to identify the next driven input level.
Programmable Pull-Up Resistor
Each Cyclone II device I/O pin provides an optional programmable
pull-up resistor during user mode. If you enable this feature for an I/O
pin, the pull-up resistor (typically 25 kΩ) holds the output to the V
level of the output pin’s bank.
1
CCIO
voltage level driven through the resistor and overdrive current
If the bus-hold feature is enabled, the device cannot use the
programmable pull-up option. Disable the bus-hold feature
when the I/O pin is configured for differential signals. Bus hold
circuitry is not available on the dedicated clock pins.
If the programmable pull-up is enabled, the device cannot use
the bus-hold feature. The programmable pull-up resistors are
not supported on the dedicated configuration, JTAG, and
dedicated clock pins.
Cyclone II Device Handbook, Volume 1
CCIO
to prevent overdriving
Cyclone II Architecture
BH
CCIO
2–51
) of