ep2c35 Altera Corporation, ep2c35 Datasheet - Page 157

no-image

ep2c35

Manufacturer Part Number
ep2c35
Description
Cyclone Ii Device Family Data Sheet
Manufacturer
Altera Corporation
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ep2c35F484
Manufacturer:
ALTERA
Quantity:
1 235
Part Number:
ep2c35F484
Manufacturer:
ALTERA
0
Part Number:
ep2c35F48418NK
Manufacturer:
ALTERA
0
Part Number:
ep2c35F484C6
Manufacturer:
Altera
Quantity:
10 000
Part Number:
ep2c35F484C6
Manufacturer:
ALTERA
0
Part Number:
ep2c35F484C6N
Manufacturer:
ALTERA
Quantity:
591
Part Number:
ep2c35F484C6N
Manufacturer:
Altera
Quantity:
10 000
Part Number:
ep2c35F484C6N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Company:
Part Number:
ep2c35F484C6N
Quantity:
1 000
Part Number:
ep2c35F484C7
Manufacturer:
ALTERA
Quantity:
300
Part Number:
ep2c35F484C7
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Part Number:
ep2c35F484C7ES
Manufacturer:
OKI
Quantity:
45 725
Part Number:
ep2c35F484C7ES
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Part Number:
ep2c35F484C7N
Manufacturer:
ALTERA
Quantity:
465
Duty Cycle
Distortion
Figure 5–8. Duty Cycle Distortion
Altera Corporation
February 2008
Notes to
(1)
(2)
(3)
(4)
(5)
(6)
f
t
V C O
A R E S E T
Table 5–54. PLL Specifications
These numbers are preliminary and pending silicon characterization.
The t
of them are switching outputs, how much they toggle, and whether or not they use programmable current strength.
If the VCO post-scale counter = 2, a 300- to 500-MHz internal VCO frequency is available.
This parameter is limited in the Quartus II software by the I/O maximum frequency. The maximum I/O frequency
is different for each I/O standard.
Cyclone II PLLs can track a spread-spectrum input clock that has an input jitter within ±200 ps.
For extended temperature devices, the maximum lock time is 500 us.
(3)
Symbol
Table
JITTER
specification for the PLL[4..1]_OUT pins are dependent on the I/O pins in its VCCIO bank, how many
5–54:
PLL internal VCO operating range
Minimum pulse width on
Duty cycle distortion (DCD) describes how much the falling edge of a
clock is off from its ideal position. The ideal position is when both the
clock high time (CLKH) and the clock low time (CLKL) equal half of the
clock period (T), as shown in
non-ideal falling edge from the ideal falling edge, such as D1 for the
falling edge A and D2 for the falling edge B
DCD for a clock is the larger value of D1 and D2.
DCD expressed in absolution derivation, for example, D1 or D2 in
Figure
percentage, and the percentage number is clock-period dependent. DCD
as a percentage is defined as:
Note (1)
CLKH = T/2
5–8, is clock-period independent. DCD can also be expressed as a
Falling Edge A
Parameter
(Part 2 of 2)
Ideal Falling Edge
Clock Period (T)
areset
D1
D2
Falling Edge B
signal.
DC Characteristics and Timing Specifications
Figure
CLKL = T/2
Cyclone II Device Handbook, Volume 1
5–8. DCD is the deviation of the
Min
300
10
(Figure
Typ
5–8). The maximum
1,000
Max
MHz
Unit
ns
5–67

Related parts for ep2c35