saf3560 NXP Semiconductors, saf3560 Datasheet - Page 10

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saf3560

Manufacturer Part Number
saf3560
Description
Terrestial Digital Radio Processor
Manufacturer
NXP Semiconductors
Datasheet

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NXP Semiconductors
SAF3560_SDS_2
Product data sheet
Table 9.
[1]
Table 10.
[1]
Table 11.
Symbol
SDRAM_AO5
SDRAM_AO4
SDRAM_AO3
SDRAM_AO2
SDRAM_AO1
SDRAM_AO0
Control interface
SDRAM_BA1
SDRAM_BA0
SDRAM_CAS_N
SDRAM_CLK
SDRAM_CLKE
SDRAM_CLKIN
SDRAM_CS_N
SDRAM_DQM1
SDRAM_DQM0
SDRAM_RAS_N
SDRAM_WE_N
Symbol
SPI2 interface
SPI2_MI
SPI2_MO
SPI2_SCLK
SPI2_SS1_N 19
SPI2_SS2_N 20
SPI2_SS3_N 22
SPI2_SS4_N 23
Symbol
CLKOUT
RESET_N
I
I2C2_DA
I2C2_SCL
I2C2_SDA
2
C-bus interface (master and slave)
Table 15
Table 15
Pin description (SDRAM interface)
Pin description (serial NOR-Flash interface)
Pin description (external host microcontroller interface)
defines the pin type.
defines the pin type.
16
17
18
2
9
7
8
Pin
Pin
1
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Pin
117
115
114
113
110
104
103
108
127
109
128
105
100
99
106
98
111
IZU
OZD
OZU
OZU
OZU
OZU
OZU
IOZD-H data acknowledge input and output of the I
IOZU
IOZU
Type
Type
OL
IZU-H
Rev. 02 — 3 May 2010
OZU
OZU
OZU
OZU
OZU
OL
OZU
Type
OZU
OZU
OZU
OZU
OZU
OZU
OZU
IZU
OL
OZU
[1]
[1]
Description
master input of second SPI interface
master output of second SPI interface
serial clock output of second SPI interface
slave select 1 output of second SPI interface (active LOW)
slave select 2 output of second SPI interface (active LOW)
slave select 3 output of second SPI interface (active LOW)
slave select 4 output of second SPI interface (active LOW)
Description
programmable through software
serial clock input and output of the I
serial data input and output of the I
[1]
clock output; clock source and clock frequency are
master reset input from host microcontroller (active LOW)
bit 1 of bank address output
bit 0 of bank address output
clock enable output
MSByte of data qualifier mask output
LSByte of data qualifier mask output
write enable output (active LOW)
Description
address output bit 5
address output bit 4
address output bit 3
address output bit 2
address output bit 1
address output bit 0
column address selector output (active LOW)
clock output
clock input for re-synchronization
chip select output (active LOW)
row address selector output (active LOW)
…continued
Terrestial digital radio processor
2
2
C-bus interface 2
C-bus interface 2
SAF3560
2
© NXP B.V. 2010. All rights reserved.
C-bus interface 2
10 of 20

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