saa7130hl-v1 NXP Semiconductors, saa7130hl-v1 Datasheet - Page 18

• Manufacturer Part Number: saa7130hl-v1
• Description: Pci Video Broadcast Decoder
• Manufacturer: NXP Semiconductors

Philips Semiconductors
SAA7130HL_4
Product data sheet
6.4.3 DMA and configurable FIFO
6.4.4 Virtual and physical addressing
Table 13:
The SAA7130HL supports seven DMA channels to master-write captured active video,
raw VBI and DTV/DVB Transport Streams (TS) into the PCI memory. Each DMA channel
contains inherently the definition of two buffers, e.g. for odd and even fields in case of
interlaced video.
The DMA channels share in time and space one common FIFO pool of 256 Dwords
(1024 bytes) total. It is freely configurable how much FIFO capacity can be associated
with which DMA channel. Furthermore, a preferred minimum burst length can be
programmed, i.e. the amount of data to be collected before the request for the PCI-bus is
issued. This means that latency behavior per DMA channel can be tailored and optimized
for a given application.
In the event that a FIFO of a certain channel overflows due to latency conflict on the bus,
graceful overflow recovery is applied. The amount of data that gets lost because it could
not be transmitted, is monitored (counted) and the PCI-bus address pointer is
incremented accordingly. Thus new data will be written to the correct memory place, after
the latency conflict is resolved.
Most operating systems allocate memory to requesting applications for DMA as
continuous ranges in virtual address space. The data flow over the PCI-bus points to
physical addresses, usually not continuous and split in pages of 4 kB (Intel architecture,
most UNIX systems, Power PC).
The association between the virtual (logic) address space and the fragmented physical
address space is defined in page tables (system files); see
The SAA7130HL incorporates hardware support (MMU) to translate virtual to physical
addresses on the fly, by investigating the related page table information. This hardware
support reduces the demand for real-time software interaction and interrupt requests, and
therefore saves system resources.
Power state
D0
D1
D2
D3-hot
Power management table
Description
Normal operation: all functions accessible and programmable. The default setting
after reset and before driver interaction (D0 un-initialized) switches most of the
circuitry of the SAA7130HL into the Power-down mode, effectively such as
D3-hot.
First step of reduced power consumption: no functional operation. Program
registers are not accessible, but content is maintained. Most of the circuitry of the
SAA7130HL is disabled with exception of the crystal and real-time clock
oscillators, so that a quick recovery from D1 to D0 is possible.
Second step of reduced power consumption: no functional operation. Program
registers are not accessible, but content is maintained. All functional circuitry of
the SAA7130HL is disabled, including the crystal and clock oscillators.
Lowest power consumption: no functional operation. The content of the
programming registers gets lost and is set to default values when returning to D0.
Rev. 04 — 11 April 2006
PCI video broadcast decoder
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Figure
SAA7130HL
8.
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