saa7105h-v1 NXP Semiconductors, saa7105h-v1 Datasheet - Page 30
saa7105h-v1
Manufacturer Part Number
saa7105h-v1
Description
Digital Video Encoder
Manufacturer
NXP Semiconductors
Datasheet
1.SAA7105H-V1.pdf
(71 pages)
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Philips Semiconductors
Table 27 Subaddress 1BH
Table 28 Subaddresses 26H and 27H
Table 29 Subaddress 28H
2004 Mar 04
MSM
MSA
MSOE
RCOMP
(read only)
GCOMP
(read only)
BCOMP
(read only)
WSS
WSSON
BS
DATA BYTE
DATA BYTE
DATA BYTE
Digital video encoder
LEVEL
LEVEL
LEVEL
LOGIC
LOGIC
LOGIC
0
1
0
1
0
1
0
1
0
1
0
1
0
1
monitor sense mode off; RCOMP, GCOMP and BCOMP bits are not valid; default after reset
monitor sense mode on
automatic monitor sense mode off; RCOMP, GCOMP and BCOMP bits are not valid; default
after reset
automatic monitor sense mode on if MSM = 0
pin TVD is active
pin TVD is 3-state; default after reset
check comparator at DAC on pin RED_CR_C_CVBS is active, output is loaded
check comparator at DAC on pin RED_CR_C_CVBS is inactive, output is not loaded
check comparator at DAC on pin GREEN_VBS_CVBS is active, output is loaded
check comparator at DAC on pin GREEN_VBS_CVBS is inactive, output is not loaded
check comparator at DAC on pin BLUE_CB_CVBS is active, output is loaded
check comparator at DAC on pin BLUE_CB_CVBS is inactive, output is not loaded
wide screen signalling bits
wide screen signalling output is disabled; default after reset
wide screen signalling output is enabled
starting point of burst in clock cycles
3 to 0 = aspect ratio
7 to 4 = enhanced services
10 to 8 = subtitles
13 to 11 = reserved
DESCRIPTION
30
DESCRIPTION
DESCRIPTION
PAL: BS = 33 (21H); default after reset if
strapping pin FSVGC tied to HIGH
NTSC: BS = 25 (19H); default after reset if
strapping pin FSVGC tied to LOW
SAA7104H; SAA7105H
REMARKS
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