saf7118 NXP Semiconductors, saf7118 Datasheet - Page 132

• Manufacturer Part Number: saf7118
• Description: Multistandard Video Decoder With Adaptive Comb Filter And Component Video Input
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Table 105: ADC port control; global set 88h[7:4]
[1]
[2]
Table 106: Power save control; global set 88h[3] and 88h[1:0]
[1]
Table 107: Status information scaler part; 8Fh[7:0]; read only register
SAF7118_3
Product data sheet
ADC port output control/start-up control
DPROG = 0 after reset
DPROG = 1 can be used to assign that the device has been
programmed; this bit can be monitored in the scalers status byte,
bit PRDON; if DPROG was set to logic 1 and PRDON status bit shows a
logic 0 a power-up or start-up fail has occurred
Scaler path is reset to its idle state, software reset
Scaler is switched back to operation
Digitized ADC1 signal is fed to port ADP[8:0]
Digitized ADC2 signal is fed to port ADP[8:0]
Digitized ADC3 signal is fed to port ADP[8:0]
Digitized ADC4 signal is fed to port ADP[8:0]
Power save control
Decoder and VBI slicer are in operational mode
Decoder and VBI slicer are in Power-down mode; scaler only operates, if
scaler input and ICLK source is the X port (refer to subaddresses
80h and 91h/C1h)
Scaler is in operational mode
Scaler is in Power-down mode; scaler in power-down stops I port output
Audio clock generation active
Audio clock generation in power-down and output disabled
Bit
D7
D6
D5
D4
D3
X = don’t care.
Bit SWRST is now located here.
X = don’t care.
I
XTRI
ITRI
FFIL
FFOV
PRDON
2
C-bus status bit
10.7.3 Subaddress 88h
10.7.4 Subaddress 8Fh
Function
status on input pin XTRI, if not used for 3-state control, usable as hardware flag
for software use
status on input pin ITRI, if not used for 3-state control, usable as hardware flag
for software use
status of the internal ‘FIFO almost filled’ flag
status of the internal ‘FIFO overflow’ flag
copy of bit DPROG, can be used to detect power-up and start-up fails
Rev. 03 — 16 February 2006
[1]
[1]
Multistandard video decoder with adaptive comb filter
[1]
Control bits D7 to D4
DOSL1
X
X
X
X
0
0
1
1
Control bits D3, D1 and D0
SLM3
X
X
X
X
0
1
DOSL0
X
X
X
X
0
1
0
1
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
SLM1
X
X
0
1
X
X
SWRST
X
X
0
1
X
X
X
X
SAF7118
SLM0
0
1
X
X
X
X
[2]
DPROG
0
1
X
X
X
X
X
X
132 of 170