dsp56004 Freescale Semiconductor, Inc, dsp56004 Datasheet - Page 50

• Manufacturer Part Number: dsp56004
• Description: Symphonytm Audio Dsp Family 24-bit Digital Signal Processors
• Manufacturer: Freescale Semiconductor, Inc

Note:
No.
163 First SCK Edge to
Specifications
Serial Host Interface (SHI) SPI Protocol Timing
2-26
SCK (CPOL = 0)
SCK (CPOL = 1)
HREQ In Not Asserted
(HREQ In Hold Time)
1.
2.
3.
4.
Characteristics
(Output)
For an Internal Clock frequency below 33 MHz, the minimum permissible Internal Clock to Serial Clock
frequency ratio is 4:1. For an Internal Clock frequency above 33 MHz, the minimum permissible Internal Clock
to Serial Clock frequency ratio is 6:1.
In CPHA = 1 mode, the SPI slave supports data transfers at t
is written at least T
supports data transfers at t
the first edge of SCK of each word.
When CPHA = 1, the SS line may remain active low between successive transfers.
Periodically sampled, not 100% tested
(Output)
(Output)
(Input)
(Input)
(Input)
HREQ
MISO
MOSI
Table 2-12 Serial Host Interface (SHI) SPI Protocol Timing (Continued)
SS
161
148
master
Mode
C
Figure 2-17 SPI Master Timing (CPHA = 0)
ns before the first edge of SCK of each word.In CPHA = 1 mode, the SPI slave
Freescale Semiconductor, Inc.
142
143
For More Information On This Product,
SPICC
Valid
MSB
Mode
Filter
MSB
= 3
DSP56004/D, Rev. 3
152
142
Go to: www.freescale.com
143
T
C
, if the user assures that the HTX is written at least T
Expression
149
163
0
144
144
148
SPICC
Min Max Min Max Min
50 MHz
0
= 3
—
Valid
LSB
T
141
141
C
153
, if the user assures that the HTX
66 MHz
0
LSB
144
144
—
149
MOTOROLA
81 MHz
0
C
Max
ns before
—
AA0271
Unit
ns