dsp56004 Freescale Semiconductor, Inc, dsp56004 Datasheet - Page 11

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dsp56004

Manufacturer Part Number
dsp56004
Description
Symphonytm Audio Dsp Family 24-bit Digital Signal Processors
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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EXTERNAL MEMORY INTERFACE (EMI)
MOTOROLA
MA0–MA14
MA15
MCS3
MA16
MCS2
MCAS
MA17
MCS1
MRAS
MCS0
MWR
MRD
Signal Name
Output
Output
Output
Output
Output
Output
Output
Signal
Type
Freescale Semiconductor, Inc.
Table 1-5 External Memory Interface (EMI) Signals
For More Information On This Product,
State during
Table 1-6
Table 1-6
Table 1-6
Table 1-6
Table 1-6
Table 1-6
Table 1-6
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DSP56004/D, Rev. 3
Memory Address Lines 0–14—The MA0–MA10 lines provide
the multiplexed row/column addresses for DRAM accesses.
Lines MA0–MA14 provide the non-multiplexed address lines
0–14 for SRAM accesses.
Memory Address Line 15 (MA15)—This line functions as the
non-multiplexed address line 15.
Memory Chip Select 3 (MCS3)—For SRAM accesses, this line
functions as memory chip select 3.
Memory Address Line 16 (MA16)—This line functions as the
non-multiplexed address line 16 or as memory chip select 2 for
SRAM accesses.
Memory Chip Select 2 (MCS2)—For SRAM access, this line
functions as memory chip select 2.
Memory Column Address Strobe (MCAS)—This line
functions as the Memory Column Address Strobe (MCAS)
during DRAM accesses.
Memory Address Line 17 (MA17)—This line functions as the
non-multiplexed address line 17.
Memory Chip Select 1 (MCS1)—This line functions as chip
select 1 for SRAM accesses.
Memory Row Address Strobe (MRAS)—This line also
functions as the Memory Row Address Strobe during DRAM
accesses.
Memory Chip Select 0—This line functions as memory chip
select 0 for SRAM accesses.
Memory Write Strobe—This line is asserted when writing to
external memory.
Memory Read Strobe—This line is asserted when reading
external memory.
Signal Description
External Memory Interface (EMI)
Signal/Connection Descriptions
1-5

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