dsp56857 Freescale Semiconductor, Inc, dsp56857 Datasheet - Page 7

• Manufacturer Part Number: dsp56857
• Description: Dsp56857 Digital Signal Controller
• Manufacturer: Freescale Semiconductor, Inc

Part 2 Signal/Connection Descriptions
2.1 Introduction
The input and output signals of the 56857 are organized into functional groups, as shown in
as illustrated in
present.
Freescale Semiconductor
1. V
2. MODE A, MODE B and MODE C can be used as GPIO after the bootstrap process has completed.
3. The following Host Interface signals are multiplexed: HRWB to HRD, HDS to HWR, HREQ to HTRQ and HACK to HRRQ.
DD
= V
DD CORE,
Power (V
Ground (V
PLL and Clock
Chip Select Logic used as dedicated GPIO
Interrupt and Program Control
Host Interface (HI)*
Enhanced Synchronous Serial Interface (ESSI0) Port*
Enhanced Synchronous Serial Interface (ESSI1) Port*
Serial Communications Interface (SCI0) Ports*
Serial Communications Interface (SCI1) Ports*
Serial Peripheral Interface (SPI) Port*
Quad Timer Module Port*
JTAG/Enhanced On-Chip Emulation (EOnCE)
*Alternately, GPIO pins
Figure
V
SS
DD,
= V
SS,
SS CORE,
2-1. In
V
V
DDIO, or
SSIO,
Table 2-1 Functional Group Pin Allocations
or V
V
Table 3-1
V
DDIO
DDA
SSA
= V
)
)
Functional Group
DD IO,
56857 Technical Data, Rev. 6
each table row describes the package pin and the signal or signals
V
SSIO
= V
SS IO,
V
DDA
= V
DD ANA,
V
SSA
= V
SS ANA
Number of Pins
(8, 12, 1)
(5, 12, 2)
16
7
3
4
6
6
2
2
4
4
6
2
3
1
1
Table 2-1
Introduction
and
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