dsp56857 Freescale Semiconductor, Inc, dsp56857 Datasheet - Page 19

• Manufacturer Part Number: dsp56857
• Description: Dsp56857 Digital Signal Controller
• Manufacturer: Freescale Semiconductor, Inc

Freescale Semiconductor
Pin No.
Table 3-1 56857 Signal and Package Information for the 100-pin LQFP (Continued)
20
21
26
44
42
41
43
3
4
Signal Name
GPIOF2
GPIOF3
EXTAL
CLKO
XTAL
TDO
TMS
SCK
TCK
TDI
SS
Input/Output
Input/Output
Input/Output
Input/Output
Output(Z)
Output
Input
Type
Input
Input
Input
Input
56857 Technical Data, Rev. 6
SPI Serial Clock (SCK)—This bidirectional pin provides a serial bit rate
clock for the SPI. This gated clock signal is an input to a slave device and
is generated as an output by a master device. Slave devices ignore the
SCK signal unless the SS pin is active low. In both master and slave SPI
devices, data is shifted on one edge of the SCK signal and is sampled on
the opposite edge where data is stable. The driver on this pin can be
configured as an open-drain driver by the SPI’s WOM bit when this pin is
configured for SPI operation. When using Wired-OR mode, the user must
provide an external pull-up device.
Port F GPIO (2)—This pin is a General Purpose I/O (GPIO) pin that can
individually be programmed as input or output pin.
SPI Slave Select (SS)—This input pin selects a slave device before a
master device can exchange data with the slave device. SS must be low
before data transactions and must stay low for the duration of the
transaction. The SS line of the master must be held high.
Port F GPIO (3)—This pin is a General Purpose I/O (GPIO) pin that can
individually be programmed as input or output pin.
Crystal Oscillator Output (XTAL)—This output connects the internal
crystal oscillator output to an external crystal. If an external clock source
other than a crystal oscillator is used, XTAL must be used as the input.
External Crystal Oscillator Input (EXTAL)—This input should be
connected to an external crystal. If an external clock source other than a
crystal oscillator is used, EXTAL must be tied off. See
Clock Output (CLKO)—This pin outputs a buffered clock signal. When
enabled, this signal is the system clock divided by four.
Test Clock Input (TCK)—This input pin provides a gated clock to
synchronize the test logic and to shift serial data to the JTAG/Enhanced
OnCE port. The pin is connected internally to a pull-down resistor.
Test Data Input (TDI)—This input pin provides a serial input data stream
to the JTAG/Enhanced OnCE port. It is sampled on the rising edge of
TCK and has an on-chip pull-up resistor.
Test Data Output (TDO)—This tri-statable output pin provides a serial
output data stream from the JTAG/Enhanced OnCE port. It is driven in
the Shift-IR and Shift-DR controller states, and changes on the falling
edge of TCK.
Test Mode Select Input (TMS)—This input pin is used to sequence the
JTAG TAP controller’s state machine. It is sampled on the rising edge of
TCK and has an on-chip pull-up resistor.
Note:
Always tie the TMS pin to V
Description
DD
through a 2.2K resistor.
Section 4.5.2
Introduction
19