dsp56362 Freescale Semiconductor, Inc, dsp56362 Datasheet - Page 86

• Manufacturer Part Number: dsp56362
• Description: Dsp56362 24-bit Audio Digital Signal Processor
• Manufacturer: Freescale Semiconductor, Inc

Serial Host Interface (SHI) I
3.13.1
The programmed serial clock cycle, T
the HCKR (SHI clock control register).
The expression for T
where:
In I
to
The programmed serial clock cycle (T
in order to achieve the desired SCL frequency, as shown in
3-60
Note: R
187
188
No.
2
C mode, the user may select a value for the programmed serial clock cycle from
HRS is the prescaler rate select bit.
HDM[7:0] are the divider modulus select bits.
A divide ratio from 1 to 64 (HDM[5:0] = 0 to $3F) may be selected.
P
Last SCL edge to HREQ output not
deasserted
Filters bypassed
Narrow filters enabled
Wide filters enabled
HREQ in assertion to first SCL edge
Filters bypassed
Narrow filters enabled
Wide filters enabled
(min) = 1.5 k¾
When HRS is cleared, the fixed divide-by-eight prescaler is operational.
When HRS is set, the prescaler is bypassed.
Programming the Serial Clock
Characteristics
T
I
2
I
CCP
2
CCP
2
C Protocol Timing
is
4096
Table 3-22 SHI I
=
6
[
×
T
×
T
C
C
T
×
(
C
I2CCP
DSP56362 Technical Data, Rev. 4
if HDM 5 0 :
I
2
(
2
if HDM 7 0 :
CCP
×
(
HDM 7 0 :
), SCL rise time (T
, is specified by the value of the HDM[5:0] and HRS bits of
2
C Protocol Timing (continued)
Standard I
2
0.5
[
0.5
Expression
2
2
×
Symbol/
[
T
×
×
T
[
AS;RQO
×
×
T
AS;RQI
T
T
C
—
]
T
T
C
C
+ 135
C
I
]
=
2
+ 30
+ 80
]
CCP
- 21
=
$
+
2
02 and HRS
C*
$
1
FF and HRS
)
Table 3-23
×
4327
4282
4238
Min
100
155
R
50
(
), and the filters selected should be chosen
Standard
7
×
1 (
Max
—
—
—
—
—
—
–
=
HRS )
=
1
)
0
)
+
1
Min
100
155
927
882
838
50
Fast-Mode
)
]
Freescale Semiconductor
Max
—
—
—
—
—
—
Unit
ns
ns